Search results for: Field effect transistor.

Authors: Hardik Vaghela, Mamta Khosla, Balwindar Raj

Abstract:

In this paper, we present and investigate a double gate PN diode based tunnel field effect transistor (DGPNTFET). The importance of proposed structure is that the formation of different drain doping is not required and ambipolar effect in OFF state is completely removed for this structure. Validation of this structure to behave like a Tunnel Field Effect Transistor (TFET) is carried out through energy band diagrams and transfer characteristics. Simulated result shows point subthreshold slope (SS) of 19.14 mV/decade and ON to OFF current ratio (I_ON / I_OFF) of 2.66 × 10¹⁴ (I_ON at V_GS=1.5V, V_DS=1V and I_OFF at V_GS=0V, V_DS=1V) for gate length of 20nm and HfO₂ as gate oxide at room temperature. Which indicate that the DGPNTFET is a promising candidate for nano-scale, ambipolar free switch.

Keywords: Ambipolar effect, double gate PN diode based tunnel field effect transistor, high-κ dielectric material, subthreshold slope, tunnel field effect transistor.

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Authors: Sang Hoon Lee, Tae Il Lee, Su Jeong Lee, Jae Min Myoung

Abstract:

In order to manufacture short gap single Si nanowire (NW) field effect transistor (FET) by imprinting and transferring method, we introduce the method using Al2O3 sacrificial layer. The diameters of cylindrical Si NW addressed between Au electrodes by dielectrophoretic (DEP) alignment method are controlled to 106, 128, and 148 nm. After imprinting and transfer process, cylindrical Si NW is embedded in PVP adhesive and dielectric layer. By curing transferred cylindrical Si NW and Au electrodes on PVP-coated p++ Si substrate with 200nm-thick SiO2, 3μm gap Si NW FET fabrication was completed. As the diameter of embedded Si NW increases, the mobility of FET increases from 80.51 to 121.24 cm2/V·s and the threshold voltage moves from –7.17 to –2.44 V because the ratio of surface to volume gets reduced.

Keywords: Al2O3 Sacrificial transfer layer, cylindrical silicon nanowires, Dielectrophorestic alignment, Field effect transistor.

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Authors: Fatima Zohra Rahou, A. Guen Bouazza, B. Bouazza

Abstract:

Invention of transistor is the foundation of electronics industry. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been the key for the development of nanoelectronics technology. In the first part of this manuscript, we present a new generation of MOSFET transistors based on SOI (Silicon-On-Insulator) technology. It is a partially depleted Silicon-On-Insulator (PD SOI MOSFET) transistor simulated by using SILVACO software. This work was completed by the presentation of some results concerning the influence of parameters variation (channel length L and gate oxide thickness Tox) on our PDSOI n-MOSFET structure on its drain current and kink effect.

Keywords: SOI technology, PDSOI MOSFET, FDSOI MOSFET, Kink Effect, SILVACO TCAD.

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Authors: Mohini Polimetla, Rajat Mahapatra

Abstract:

There is need to explore emerging technologies based on carbon nanotube electronics as the MOS technology is approaching its limits. As MOS devices scale to the nano ranges, increased short channel effects and process variations considerably effect device and circuit designs. As a promising new transistor, the Carbon Nanotube Field Effect Transistor(CNTFET) avoids most of the fundamental limitations of the Traditional MOSFET devices. In this paper we present the analysis and comparision of a Carbon Nanotube FET(CNTFET) based 10(A current mirror with MOSFET for 32nm technology node. The comparision shows the superiority of the former in terms of 97% increase in output resistance,24% decrease in power dissipation and 40% decrease in minimum voltage required for constant saturation current. Furthermore the effect on performance of current mirror due to change in chirality vector of CNT has also been investigated. The circuit simulations are carried out using HSPICE model.

Keywords: Carbon Nanotube Field Effect Transistor, Chirality Vector, Current Mirror

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Authors: O. L. Kukla, S. V. Marchenko, O. A. Zinchenko, O. S. Pavluchenko, O. M. KKuukla, S. V. Dzyadevych, O. P. Soldatkin

Abstract:

An application of the highly biosensor based on pH-sensitive field immobilized urease for urea analysis was demo The main analytical characteristics of the bios determined; the conditions of urea measureme blood were optimized. A conceptual possibility biosensor for detection of urea concentratio patients suffering from renal insufficiency was sensitive and selective effect transistor and monstrated in this work. iosensor developed were ment in real samples of ility of application of the tion in blood serum of as shown.

Keywords: Biosensor, blood serum, pH transistor, urea, urease, field-effect

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Authors: Jae-Hong Kwon, Myung-Ho Chung, Tae-Yeon Oh, Hyeon-Seok Bae, Byeong-Kwon Ju

Abstract:

End-substitution of quarterthiophene and sexithiophene with hexyl groups leads to highly soluble conjugated oligomers,DZ-dihexylquarterthiophene (DH-4T) and DZ-dihexylsexithiophene (DH-6T). We have characterized these oligomers for optical and electrical properties. We fabricated an organic thin film transistor (OTFT) using the above two air-stable p-type organic semiconductor materials. We obtained a stable characteristic curve. The field effect mobility, Pwas calculated to be 3.2910-4 cm2/Vs for DH-6T based OTFT; while the DH-4T based OTFT had 1.8810-5 cm2/Vs.KeywordsOrganic thin film transistor, DZ-dihexylquarterthiophene, DZ-dihexylsexithiophene.

Keywords: Organic thin film transistor, DZ-dihexylquarterthiophene, DZ-dihexylsexithiophene.

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Authors: Q. Zafar, R. Akram, Kh.S. Karimov, T.A. Khan, M. Farooq, M.M. Tahir

Abstract:

In this study we present the effect of elevated temperatures from 300K to 400K on the electrical properties of copper Phthalocyanine (CuPc) based organic field effect transistors (OFET). Thin films of organic semiconductor CuPc (40nm) and semitransparent Al (20nm) were deposited in sequence, by vacuum evaporation on a glass substrate with previously deposited Ag source and drain electrodes with a gap of 40 μm. Under resistive mode of operation, where gate was suspended it was observed that drain current of this organic field effect transistor (OFET) show an increase with temperature. While in grounded gate condition metal (aluminum) – semiconductor (Copper Phthalocyanine) Schottky junction dominated the output characteristics and device showed switching effect from low to high conduction states like Zener diode at higher bias voltages. This threshold voltage for switching effect has been found to be inversely proportional to temperature and shows an abrupt decrease after knee temperature of 360K. Change in dynamic resistance (Rd = dV/dI) with respect to temperature was observed to be -1%/K.

Keywords: Copper Phthalocyanine, Metal-Semiconductor Schottky Junction, Organic Field Effect Transistor, Switching effect, Temperature Sensor

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Authors: Yashvir Singh, Swati Chamoli

Abstract:

In this paper, a power laterally-diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) on In_0.53Ga_0.47As is presented. The device utilizes a thicker field-oxide with low dielectric constant under the field-plate in order to achieve possible reduction in device capacitances and reduced-surface-field effect. Using 2D numerical simulations, performance of the proposed device is analyzed and compared with that of the conventional LDMOSFET. The proposed structure provides 50% increase in the breakdown voltage, 21% increase in transit frequency, and 72% improvement in figure-of-merit over the conventional device for same cell pitch.

Keywords: InGaAs, dielectric, lateral, power MOSFET.

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Authors: Mehdi Saeidmanesh, Razali Ismail

Abstract:

Recently, Graphene Nanoribbon Field Effect Transistors (GNR FETs) attract a great deal of attention due to their better performance in comparison with conventional devices. In this paper, channel length Modulation (CLM) effect on the electrical characteristics of GNR FETs is analytically studied and modeled. To this end, the special distribution of the electric potential along the channel and current-voltage characteristic of the device is modeled. The obtained results of analytical model are compared to the experimental data of published works. As a result, it is observable that considering the effect of CLM, the current-voltage response of GNR FET is more realistic.

Keywords: Graphene nanoribbon, field effect transistors, short channel effects, channel length modulation.

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Authors: Shubhajit Roy Chowdhury, Aritra Banerjee, Aniruddha Roy, Hiranmay Saha

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The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three-transistor XOR gate and its performance has been investigated using 0.15um and 0.35um technologies. Compared to the earlier designed 10 transistor full adder, the proposed adder shows a significant improvement in silicon area and power delay product. The whole simulation has been carried out using HSPICE.

Keywords: XOR gate, full adder, improvement in speed, area minimization, transistor count minimization.

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Authors: Su Jeong Lee, Tae Il Lee, Jung Han Kim, Chul-Hong Kim, Gee Sung Chae, Jae-Min Myoung

Abstract:

The contact resistance between source/drain electrodes and semiconductor layer is an important parameter affecting electron transporting performance in the thin film transistor (TFT). In this work, we introduced a transparent and the solution prossable single-walled carbon nanotube (SWCNT)/Al-doped ZnO nano particle (AZO NP) bilayer electrodes showing low contact resistance with indium-oxide (In2O3) sol gel thin film. By inserting low work function AZO NPs into the interface between the SWCNTs and the In2O3 which has a high energy barrier, we could obtain an electrical Ohmic contact between them. Finally, with the SWCNT-AZO NP bilayer electrodes, we successfully fabricated a TFT showing a field effect mobility of 5.38 cm2/V·s at 250°C.

Keywords: Single-walled carbon nanotube (SWCNT), Al-doped ZnO (AZO) nanoparticle, contact resistance, Thin-film transistor (TFT).

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Authors: Abdelmonaem Ayachi, Belgacem Hamdi

Abstract:

This paper presents a fault-tolerant implementation for adder schemes using the dual duplication code. To prove the efficiency of the proposed method, the circuit is simulated in double pass transistor CMOS 32nm technology and some transient faults are voluntary injected in the Layout of the circuit. This fully differential implementation requires only 20 transistors which mean that the proposed design involves 28.57% saving in transistor count compared to standard CMOS technology.

Keywords: Semiconductors, digital electronics, double pass transistor technology, Full adder, fault tolerance.

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Authors: Yuzman Yusoff, Siti Noor Harun, Noor Shelida Sallehand Tan Kong Yew

Abstract:

This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan.

Keywords: Readout interface circuit (ROIC), analog interface circuit, ion sensitive field effect transistor (ISFET), ion selective electrode (ISE), and ion sensor electronics.

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Authors: Yuzman Yusoff, Siti Noor Harun, Noor Shelida Sallehand, Tan Kong Yew

Abstract:

This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 Rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan.

Keywords: Readout interface circuit (ROIC), analog interface circuit, ion sensitive field effect transistor (ISFET), ion selective electrode (ISE), ion sensor electronics.

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Authors: K. E. Kaharudin, A. H. Hamidon, F. Salehuddin

Abstract:

Vertical Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is believed to suppress various short channel effect problems. The gate to channel coupling in vertical DG-MOSFET are doubled, thus resulting in higher current density. By having two gates, both gates are able to control the channel from both sides and possess better electrostatic control over the channel. In order to ensure that the transistor possess a superb turn-off characteristic, the subs-threshold swing (SS) must be kept at minimum value (60-90mV/dec). By utilizing SILVACO TCAD software, an n-channel vertical DG-MOSFET was successfully designed while keeping the sub-threshold swing (SS) value as minimum as possible. From the observation made, the value of sub-threshold swing (SS) was able to be varied by adjusting the height of the silicon pillar. The minimum value of sub-threshold swing (SS) was found to be 64.7mV/dec with threshold voltage (V_TH) of 0.895V. The ideal height of the vertical DG-MOSFET pillar was found to be at 0.265 µm.

Keywords: DG-MOSFET, pillar, SCE, vertical

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Authors: Mohammad Hosseini

Abstract:

Ultrafast transistor laser investigated here has the graded index separate confinement heterostructure (GRIN-SCH) in its base region. Resonance-free optical frequency response with -3 dB bandwidth of more than 26 GHz has been achieved for a single quantum well transistor laser by using graded index layers of AlξGa1-ξAs (ξ: 0.1→0) in the left side of quantum well and AlξGa1-ξAs (ξ: 0.05→0) in the right side of quantum well. All required parameters, including quantum well and base transit time, optical confinement factor and spontaneous recombination lifetime, have been calculated using a self-consistent charge control model.

Keywords: Transistor laser, ultrafast, GRIN-SCH, -3db optical bandwidth, AlξGa1-ξAs.

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Authors: Fatemeh Karimi, Morteza Fathipour, Hamdam Ghanatian, Vala Fathipour

Abstract:

In this paper we investigate the electrical characteristics of a new structure of gate all around strained silicon nanowire field effect transistors (FETs) with dual dielectrics by changing the radius (RSiGe) of silicon-germanium (SiGe) wire and gate dielectric. Indeed the effect of high-κ dielectric on Field Induced Barrier Lowering (FIBL) has been studied. Due to the higher electron mobility in tensile strained silicon, the n-type FETs with strained silicon channel have better drain current compare with the pure Si one. In this structure gate dielectric divided in two parts, we have used high-κ dielectric near the source and low-κ dielectric near the drain to reduce the short channel effects. By this structure short channel effects such as FIBL will be reduced indeed by increasing the RSiGe, ID-VD characteristics will be improved. The leakage current and transfer characteristics, the threshold-voltage (Vt), the drain induced barrier height lowering (DIBL), are estimated with respect to, gate bias (VG), RSiGe and different gate dielectrics. For short channel effects, such as DIBL, gate all around strained silicon nanowire FET have similar characteristics with the pure Si one while dual dielectrics can improve short channel effects in this structure.

Keywords: SNWT (silicon nanowire transistor), Tensile Strain, high-κ dielectric, Field Induced Barrier Lowering (FIBL), cylindricalnano wire (CW), drain induced barrier lowering (DIBL).

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Authors: Akash Rathee, Harish Parthasarathy

Abstract:

In this paper, a frequency-variation based method has been proposed for transistor parameter estimation in a commonemitter transistor amplifier circuit. We design an algorithm to estimate the transistor parameters, based on noisy measurements of the output voltage when the input voltage is a sine wave of variable frequency and constant amplitude. The common emitter amplifier circuit has been modelled using the transistor Ebers-Moll equations and the perturbation technique has been used for separating the linear and nonlinear parts of the Ebers-Moll equations. This model of the amplifier has been used to determine the amplitude of the output sinusoid as a function of the frequency and the parameter vector. Then, applying the proposed method to the frequency components, the transistor parameters have been estimated. As compared to the conventional time-domain least squares method, the proposed method requires much less data storage and it results in more accurate parameter estimation, as it exploits the information in the time and frequency domain, simultaneously. The proposed method can be utilized for parameter estimation of an analog device in its operating range of frequencies, as it uses data collected from different frequencies output signals for parameter estimation.

Keywords: Perturbation Technique, Parameter estimation, frequency-variation based method.

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Authors: Spyridon Nikolaidis

Abstract:

A modeling approach for CMOS gates is presented based on the use of the equivalent inverter. A new model for the inverter has been developed using a simplified transistor current model which incorporates the nanoscale effects for the planar technology. Parametric expressions for the output voltage are provided as well as the values of the output and supply current to be compatible with the CCS technology. The model is parametric according the input signal slew, output load, transistor widths, supply voltage, temperature and process. The transistor widths of the equivalent inverter are determined by HSPICE simulations and parametric expressions are developed for that using a fitting procedure. Results for the NAND gate shows that the proposed approach offers sufficient accuracy with an average error in propagation delay about 5%.

Keywords: CMOS gate modeling, Inverter modeling, transistor current model, timing model.

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Authors: N. Shen, T. T. Le, H. Y. Yu, Z. X. Chen, K. T. Win, N. Singh, G. Q. Lo, D. -L. Kwong

Abstract:

In this paper, we present a vertical nanowire thin film transistor with gate-all-around architecture, fabricated using CMOS compatible processes. A novel method of fabricating polysilicon vertical nanowires of diameter as small as 30 nm using wet-etch is presented. Both n-type and p-type vertical poly-silicon nanowire transistors exhibit superior electrical characteristics as compared to planar devices. On a poly-crystalline nanowire of 30 nm diameter, high Ion/Ioff ratio of 106, low drain-induced barrier lowering (DIBL) of 50 mV/V, and low sub-threshold slope SS~100mV/dec are demonstrated for a device with channel length of 100 nm.

Keywords: Nanowire (NW), Gate-all-around (GAA), polysilicon (poly-Si), thin-film transistor (TFT).

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Authors: Sangeeta Singh, Pankaj Kumar, P. N. Kondekar

Abstract:

In this paper, the transient device performance analysis of n-type Gate Inside JunctionLess Transistor (GI-JLT) has been evaluated. 3-D Bohm Quantum Potential (BQP) transport device simulation has been used to evaluate the delay and power dissipation performance. GI-JLT has a number of desirable device parameters such as reduced propagation delay, dynamic power dissipation, power and delay product, intrinsic gate delay and energy delay product as compared to Gate-all-around transistors GAA-JLT. In addition to this, various other device performance parameters namely, on/off current ratio, short channel effects (SCE), transconductance Generation Factor (TGF) and unity gain cut-off frequency (fT ) and subthreshold slope (SS) of the GI-JLT and GAA-JLT have been analyzed and compared. GI-JLT shows better device performance characteristics than GAA-JLT for low power and high frequency applications, because of its larger gate electrostatic control on the device operation.

Keywords: Gate-inside junctionless transistor GI-JLT, Gate-all-around junctionless transistor GAA-JLT, propagation delay, power delay product.

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Authors: Xiang Li, Zhixian Chen, Zheng Fang, Aashit Kamath, Xinpeng Wang, Navab Singh, Guo-Qiang Lo, Dim-Lee Kwong

Abstract:

We integrate TiN/Ni/HfO2/Si RRAM cell with a vertical gate-all-around (GAA) nanowire transistor to achieve compact 4F2 footprint in a 1T1R configuration. The tip of the Si nanowire (source of the transistor) serves as bottom electrode of the memory cell. Fabricated devices with nanowire diameter ~ 50nm demonstrate ultra-low current/power switching; unipolar switching with 10μA/30μW SET and 20μA/30μW RESET and bipolar switching with 20nA/85nW SET and 0.2nA/0.7nW RESET. Further, the switching current is found to scale with nanowire diameter making the architecture promising for future scaling.

Keywords: RRAM, 1T1R, gate-all-around FET, nanowire FET, vertical MOSFETs

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Authors: E. Yosry, W. Fikry, A. El-henawy, M. Marzouk

Abstract:

This work offers a study of new simple compact model of dual-drain Magnetic Field Effect Transistor (MAGFET) including geometrical effects and biasing dependency. An explanation of the sensitivity is investigated, involving carrier deflection as the dominant operating principle. Finally, model verification with simulation results is introduced to ensure that acceptable error of 2% is achieved.

Keywords: MAGFET, Modeling, Simulation, Split-drain.

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Authors: Arash Azizi Mazreah, Mohammad Reza Sahebi, Mohammad T. Manzuri Shalmani

Abstract:

To help overcome limits to the density of conventional SRAMs and leakage current of SRAM cell in nanoscaled CMOS technology, we have developed a four-transistor SRAM cell. The newly developed CMOS four-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 19% smaller than a conventional six-transistor cell using same design rules. Also the leakage current of new cell is 60% smaller than a conventional sixtransistor SRAM cell. Simulation result in 65nm CMOS technology shows new cell has correct operation during read/write operation and idle mode.

Keywords: SRAM Cell, leakage current, cell area.

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Authors: Nur Syarafina Binti Othman, Tsubasa Jindo, Makato Yamada, Miho Tsuyama, Hitoshi Nakano

Abstract:

A novel method to produce a fast high voltage solid states switch using Insulated Gate Bipolar Transistors (IGBTs) is presented for discharge-pumped gas lasers. The IGBTs are connected in series to achieve a high voltage rating. An avalanche transistor is used as the gate driver. The fast pulse generated by the avalanche transistor quickly charges the large input capacitance of the IGBT, resulting in a switch out of a fast high-voltage pulse. The switching characteristic of fast-high voltage solid state switch has been estimated in the multi-stage series-connected IGBT with the applied voltage of several tens of kV. Electrical circuit diagram and the mythology of fast-high voltage solid state switch as well as experimental results obtained are presented.

Keywords: High voltage, IGBT, Solid states switch.

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Authors: P. Asadee

Abstract:

Multiplication algorithms have considerable effect on processors performance. A new high-speed, low-power multiplication algorithm has been presented using modified Dadda tree structure. Three important modifications have been implemented in inner product generation step, inner product reduction step and final addition step. Optimized algorithms have to be used into basic computation components, such as multiplication algorithms. In this paper, we proposed a new algorithm to reduce power, delay, and transistor count of a multiplication algorithm implemented using low power modified counter. This work presents a novel design for Dadda multiplication algorithms. The proposed multiplication algorithm includes structured parts, which have important effect on inner product reduction tree. In this paper, a 1.3V, 64-bit carry hybrid adder is presented for fast, low voltage applications. The new 64-bit adder uses a new circuit to implement the proposed carry hybrid adder. The new adder using 80 nm CMOS technology has been implemented on 700 MHz clock frequency. The proposed multiplication algorithm has achieved 14 percent improvement in transistor count, 13 percent reduction in delay and 12 percent modification in power consumption in compared with conventional designs.

Keywords: adder, CMOS, counter, Dadda tree, encoder.

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Authors: Arash Azizi Mazreah, Mohammad T. Manzuri Shalmani, Hamid Barati, Ali Barati

Abstract:

This paper presents a novel CMOS four-transistor SRAM cell for very high density and low power embedded SRAM applications as well as for stand-alone SRAM applications. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 20% smaller than a conventional six-transistor cell using same design rules. Also proposed cell uses two word-lines and one pair bit-line. Read operation perform from one side of cell, and write operation perform from another side of cell, and swing voltage reduced on word-lines thus dynamic power during read/write operation reduced. The fabrication process is fully compatible with high-performance CMOS logic technologies, because there is no need to integrate a poly-Si resistor or a TFT load. HSPICE simulation in standard 0.25μm CMOS technology confirms all results obtained from this paper.

Keywords: Positive feedback, leakage current, read operation, write operation, dynamic energy consumption.

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Authors: Jianping Hu, Xiaolei Sheng

Abstract:

This paper introduces an adiabatic register file based on two-phase CPAL (Complementary Pass-Transistor Adiabatic Logic circuits) with power-gating scheme, which can operate on a single-phase power clock. A 32×32 single-phase adiabatic register file with power-gating scheme has been implemented with TSMC 0.18μm CMOS technology. All the circuits except for the storage cells employ two-phase CPAL circuits, and the storage cell is based on the conventional memory one. The two-phase non-overlap power-clock generator with power-gating scheme is used to supply the proposed adiabatic register file. Full-custom layouts are drawn. The energy and functional simulations have been performed using the net-list extracted from their layouts. Compared with the traditional static CMOS register file, HSPICE simulations show that the proposed adiabatic register file can work very well, and it attains about 73% energy savings at 100 MHz.

Keywords: Low power, Register file, Complementarypass-transistor logic, Adiabatic logic, Single-phase power clock.

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Authors: Porag Jyoti Ligira, Gargi Khanna

Abstract:

The paper presents a simulation study of the electrical characteristic of Bulk Planar Junctionless Transistor (BPJLT) using spacer. The BPJLT is a transistor without any PN junctions in the vertical direction. It is a gate controlled variable resistor. The characteristics of BPJLT are analyzed by varying the oxide material under the gate. It can be shown from the simulation that an ideal subthreshold slope of ~60 mV/decade can be achieved by using highk dielectric. The effects of variation of spacer length and material on the electrical characteristic of BPJLT are also investigated in the paper. The ION / IOFF ratio improvement is of the order of 107 and the OFF current reduction of 10-4 is obtained by using gate dielectric of HfO2 instead of SiO2.

Keywords: BPJLT, double gate, high-k, spacer.

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Authors: Ala'eddin A. Saif , Z. A. Z. Jamal, Z. Sauli, P. Poopalan

Abstract:

The ferroelectric behavior of barium strontium titanate (BST) in thin film form has been investigated in order to study the possibility of using BST for ferroelectric gate-field effect transistor (FeFET) for memory devices application. BST thin films have been fabricated as Al/BST/Pt/SiO2/Si-gate configuration. The variation of the dielectric constant (ε) and tan δ with frequency have been studied to ensure the dielectric quality of the material. The results show that at low frequencies, ε increases as the Ba content increases, whereas at high frequencies, it shows the opposite variation, which is attributed to the dipole dynamics. tan δ shows low values with a peak at the mid-frequency range. The ferroelectric behavior of the Al/BST/Pt/SiO2/Si has been investigated using C-V characteristics. The results show that the strength of the ferroelectric hysteresis loop increases as the Ba content increases; this is attributed to the grain size and dipole dynamics effect.

Keywords: BST thin film, Electrical properties, Ferroelectrichysteresis, Ferroelectric FET.

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