Transient Analysis & Performance Estimation of Gate Inside Junctionless Transistor (GI-JLT)

Authors: Sangeeta Singh, Pankaj Kumar, P. N. Kondekar

Abstract:

In this paper, the transient device performance analysis of n-type Gate Inside JunctionLess Transistor (GI-JLT) has been evaluated. 3-D Bohm Quantum Potential (BQP) transport device simulation has been used to evaluate the delay and power dissipation performance. GI-JLT has a number of desirable device parameters such as reduced propagation delay, dynamic power dissipation, power and delay product, intrinsic gate delay and energy delay product as compared to Gate-all-around transistors GAA-JLT. In addition to this, various other device performance parameters namely, on/off current ratio, short channel effects (SCE), transconductance Generation Factor (TGF) and unity gain cut-off frequency (fT ) and subthreshold slope (SS) of the GI-JLT and GAA-JLT have been analyzed and compared. GI-JLT shows better device performance characteristics than GAA-JLT for low power and high frequency applications, because of its larger gate electrostatic control on the device operation.

Keywords: Gate-inside junctionless transistor GI-JLT, Gate-all-around junctionless transistor GAA-JLT, propagation delay, power delay product.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1099000

References:

[1] J. E. Lilienfeld, “Method and apparatus for controlling electric current,” Jan.28 Jan. 28, 1930, U.S Patent 1 745 175.
[2] J.-P. Colinge, C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White et al., “Nanowire transistors without junctions,” Nature Nanotechnology, vol. 5, no. 3, pp. 225–229, 2010.
[3] J.-P. Colinge, M. Gao, A. Romano-Rodriguez, H. Maes, and C. Claeys, “Silicon-on-insulator gate-all-around device’,” in Electron Devices Meeting, 1990. IEDM’90. Technical Digest., International. IEEE, 1990, pp. 595–598.
[4] A. Kranti, R. Yan, C.-W. Lee, I. Ferain, R. Yu, N. D. Akhavan, P. Razavi, and J. Colinge, “Junctionless nanowire transistor (jnt): Properties and design guidelines,” in Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European. IEEE, 2010, pp. 357–360.
[5] R. T. Doria, M. A. Pavanello, R. D. Trevisoli, M. de Souza, C.-W. Lee, I. Ferain, N. D. Akhavan, R. Yan, P. Razavi, R. Yu et al., “Junctionless multiple-gate transistors for analog applications,” Electron Devices, IEEE Transactions on, vol. 58, no. 8, pp. 2511–2519, 2011.
[6] C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J.-P. Colinge, “Junctionless multigate field-effect transistor,” Applied Physics Letters, vol. 94, no. 5, pp. 053 511–053 511, 2009.
[7] C.-W. Lee, A. N. Nazarov, I. Ferain, N. D. Akhavan, R. Yan, P. Razavi, R. Yu, R. T. Doria, and J.-P. Colinge, “Low subthreshold slope in junctionless multigate transistors,” Applied Physics Letters, vol. 96, no. 10, pp. 102 106–102 106, 2010.
[8] S. Gundapaneni, S. Ganguly, and A. Kottantharayil, “Bulk planar junctionless transistor (BPJLT): an attractive device alternative for scaling,” Electron Device Letters, IEEE, vol. 32, no. 3, pp. 261–263, 2011.
[9] B. Sor´ee, W. Magnus, and G. Pourtois, “Analytical and self-consistent quantum mechanical model for a surrounding gate mos nanowire operated in JFET mode,” Journal of computational electronics, vol. 7, no. 3, pp. 380–383, 2008.
[10] P. Kumar, C. Sahu, A. Shrivastava, P. Kondekar, and J. Singh, “Characteristics of gate inside junctionless transistor with channel length and doping concentration,” in IEEE International conference on Electron Devices and Solid-State and Circuits (EDSSC13),, Hong Kong, Polytechnic University, 2013.
[11] P. Kumar, S. Singh, P. Kondekar, and A. Dixit, “Digital and analog performance of gate inside p-type junctionless transistor (GI-JLT),” in CIMSim2013, 5th International Conference on Computational Intelligence, Modelling and Simulation (CIMSim2013), Seoul, Korea, Sep. 2013.
[12] D. S. Atlas, “Atlas users manual,” Silvaco International Software, Santa Clara, CA, USA, 2005.
[13] A. Manual, “3-D device simulator, silvaco international, version 5.14. 0,” 2010.
[14] A. U. Manual, “Device simulation software,” SILVACO International, Santa Clara, CA, vol. 95054, p. 20, 2008.
[15] G. Mariniello, R. Doria, M. de Souza, M. Pavanello, and R. Trevisoli, “Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations,” in Devices, Circuits and Systems (ICCDCS), 2012 8th International Caribbean Conference on. IEEE, 2012, pp. 1–4.
[16] P. Razavi, I. Ferain, S. Das, R. Yu, N. D. Akhavan, and J.-P. Colinge, “Intrinsic gate delay and energy-delay product in junctionless nanowire transistors,” in Ultimate Integration on Silicon (ULIS), 2012 13th International Conference on. IEEE, 2012, pp. 125–128.