@article{(Open Science Index):https://publications.waset.org/pdf/15296,
	  title     = {A Novel Nano-Scaled SRAM Cell},
	  author    = {Arash Azizi Mazreah and  Mohammad Reza Sahebi and  Mohammad T. Manzuri Shalmani},
	  country	= {},
	  institution	= {},
	  abstract     = {To help overcome limits to the density of conventional SRAMs and leakage current of SRAM cell in nanoscaled CMOS technology, we have developed a four-transistor SRAM cell. The newly developed CMOS four-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 19% smaller than a conventional six-transistor cell using same design rules. Also the leakage current of new cell is 60% smaller than a conventional sixtransistor SRAM cell. Simulation result in 65nm CMOS technology shows new cell has correct operation during read/write operation and idle mode.
},
	    journal   = {International Journal of Electronics and Communication Engineering},
	  volume    = {4},
	  number    = {5},
	  year      = {2010},
	  pages     = {781 - 783},
	  ee        = {https://publications.waset.org/pdf/15296},
	  url   	= {https://publications.waset.org/vol/41},
	  bibsource = {https://publications.waset.org/},
	  issn  	= {eISSN: 1307-6892},
	  publisher = {World Academy of Science, Engineering and Technology},
	  index 	= {Open Science Index 41, 2010},
	}