Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 31097
A Single-Phase Register File with Complementary Pass-Transistor Adiabatic Logic

Authors: Jianping Hu, Xiaolei Sheng


This paper introduces an adiabatic register file based on two-phase CPAL (Complementary Pass-Transistor Adiabatic Logic circuits) with power-gating scheme, which can operate on a single-phase power clock. A 32×32 single-phase adiabatic register file with power-gating scheme has been implemented with TSMC 0.18μm CMOS technology. All the circuits except for the storage cells employ two-phase CPAL circuits, and the storage cell is based on the conventional memory one. The two-phase non-overlap power-clock generator with power-gating scheme is used to supply the proposed adiabatic register file. Full-custom layouts are drawn. The energy and functional simulations have been performed using the net-list extracted from their layouts. Compared with the traditional static CMOS register file, HSPICE simulations show that the proposed adiabatic register file can work very well, and it attains about 73% energy savings at 100 MHz.

Keywords: low power, Register file, Complementarypass-transistor logic, Adiabatic logic, Single-phase power clock

Digital Object Identifier (DOI):

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1627


[1] J. M. Rabaey and M. Pedram, "Low power design methodologies," Kluwer Academic Publishers, Boston, 1996, pp. 65-95.
[2] Y. Moon and D. K. Jeong, "A 32 x 32-b adiabatic register file with supply clock generator," IEEE Journal of Solid-State Circuits, vol. 33, no. 5, 1998, pp. 696 -701.
[3] K. W. Ng and K. T. Lau, "A novel adiabatic register file design," Journal of Circuits, Systems, and Computers, vol. 10, no. 1, 2000, pp. 67-76.
[4] Jianping Hu, Tiefeng Xu, and Hong Li, "A lower-power register file based on complementary pass-transistor adiabatic logic," IEICE Transactions on Information and Systems, vol. E88-D, no. 7, 2005, pp. 1479-1485.
[5] Jianping Hu, Binbin Liu, Xuanyan Hu, and Sheng Zhang, "A Test Chip for CPAL Register File Fabricated in Chartered 0.35╬╝m CMOS Process," IEEE Midwest Symposium on Circuits and Systems, 10-13 Aug. 2008, pp. 434 - 437.
[6] J. -H. Kwon, J. Lim, and S. -I. Chae, "Three-port nRERL register file for ultra-low-energy applications," The International Symposium on Low Power Electronics and Design, Digest of Technical Papers, 2000, pp. 161-166.
[7] S. Kim, C. H. Ziesler, and M. C. Papaefthymiou, "A true single-phase energy-recovery multiplier," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 2, 2003, pp.194-207.
[8] D. Maksimovic, V. G. Oklobdzija, B. Nikolic, and K. W. Current, "Clocked CMOS adiabatic logic with integrated single-phase power-clock supply," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, no. 4, 2000, pp. 460-463.
[9] D. Maksimovic and V. G. Oklobdzija, "Integrated power clock generators for low energy logic," IEEE Power Electronics Specialists Conference, Atlanta, June 1995, pp.61-67.
[10] Jianping Hu, Tiefeng Xu, and Yinshui Xia, "Low-power adiabatic sequential circuits with complementary pass-transistor logic," IEEE Midwest Symposium on Circuits and Systems, USA, August 7-10, 2005, pp. 1398-1401.
[11] H. Mahmoodi-Meimand and A. Afzali-Kusha, "Efficient power clock generation for adiabatic logic," IEEE International Symposium on Circuits and Systems, 2001, pp.642-645.
[12] Dong Zhou, Jianping Hu, and Ling Wang, "Adiabatic Flip-Flops for Power-Down Applications," IEEE International Symposium on Integrated Circuits, Singapore, 2007, pp. 493-496.