Search results for: Nanowire (NW)

Authors: Xiang Li, Zhixian Chen, Zheng Fang, Aashit Kamath, Xinpeng Wang, Navab Singh, Guo-Qiang Lo, Dim-Lee Kwong

Abstract:

We integrate TiN/Ni/HfO2/Si RRAM cell with a vertical gate-all-around (GAA) nanowire transistor to achieve compact 4F2 footprint in a 1T1R configuration. The tip of the Si nanowire (source of the transistor) serves as bottom electrode of the memory cell. Fabricated devices with nanowire diameter ~ 50nm demonstrate ultra-low current/power switching; unipolar switching with 10μA/30μW SET and 20μA/30μW RESET and bipolar switching with 20nA/85nW SET and 0.2nA/0.7nW RESET. Further, the switching current is found to scale with nanowire diameter making the architecture promising for future scaling.

Keywords: RRAM, 1T1R, gate-all-around FET, nanowire FET, vertical MOSFETs

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Authors: J. Davoodi, F. Katouzi

Abstract:

The aim of this research was to calculate the thermal properties of Au3Ni Nanowire. The molecular dynamics (MD) simulation technique was used to obtain the effect of radius size on the energy, the melting temperature and the latent heat of fusion at the isobaric-isothermal (NPT) ensemble. The Quantum Sutton-Chen (Q-SC) many body interatomic potentials energy have been used for Gold (Au) and Nickel (Ni) elements and a mixing rule has been devised to obtain the parameters of these potentials for nanowire stats. Our MD simulation results show the melting temperature and latent heat of fusion increase upon increasing diameter of nanowire. Moreover, the cohesive energy decreased with increasing diameter of nanowire.

Keywords: Au3Ni Nanowire, Thermal properties, Molecular dynamics simulation

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Authors: N. Shen, T. T. Le, H. Y. Yu, Z. X. Chen, K. T. Win, N. Singh, G. Q. Lo, D. -L. Kwong

Abstract:

In this paper, we present a vertical nanowire thin film transistor with gate-all-around architecture, fabricated using CMOS compatible processes. A novel method of fabricating polysilicon vertical nanowires of diameter as small as 30 nm using wet-etch is presented. Both n-type and p-type vertical poly-silicon nanowire transistors exhibit superior electrical characteristics as compared to planar devices. On a poly-crystalline nanowire of 30 nm diameter, high Ion/Ioff ratio of 106, low drain-induced barrier lowering (DIBL) of 50 mV/V, and low sub-threshold slope SS~100mV/dec are demonstrated for a device with channel length of 100 nm.

Keywords: Nanowire (NW), Gate-all-around (GAA), polysilicon (poly-Si), thin-film transistor (TFT).

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Authors: Z. X. Chen, T. S. Phua, X. P. Wang, G. -Q. Lo, D. -L. Kwong

Abstract:

This paper presents device simulations on the vertical silicon nanowire tunneling FET (VSiNW TFET). Simulations show that a narrow nanowire and thin gate oxide is required for good performance, which is expected even for conventional MOSFETs. The gate length also needs to be more than the nanowire diameter to prevent short channel effects. An effect more unique to TFET is the need for abrupt source to channel junction, which is shown to improve the performance. The ambipolar effect suppression by reducing drain doping concentration is also explored and shown to have little or no effect on performance.

Keywords: Device simulation, MEDICI, tunneling FET (TFET), vertical silicon nanowire.

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Authors: Amin Nekoubin, Abdolamir Nekoubin

Abstract:

Vertical ZnO nanowire array films were synthesized based on aqueous method for sensing applications. ZnO nanowires were investigated structurally using X-ray diffraction (XRD) and scanning electron microscopy (SEM). The gas-sensing properties of ZnO nanowires array films are studied. It is found that the ZnO nanowires array film sensor exhibits excellent sensing properties towards O2 and CO2 at 100 °C with the response time shorter than 5 s. High surface area / volume ratio of vertical ZnO nanowire and high mobility accounts for the fast response and recovery. The sensor response was measured in the range from 100 to 500 ppm O2 and CO2 in this study.

Keywords: Gas sensor, semiconductor, ZnO, Nanowire array

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Authors: Seyed Ali Sedigh Zyabari, A. Zarifkar

Abstract:

Single photon detectors have been fabricated NbN nano wire. These detectors are fabricated from high quality, ultra high vacuum sputtered NbN thin films on a sapphire substrate. In this work a typical schematic of the nanowire Single Photon Detector structure and then driving and measurement electronic circuit are shown. The response of superconducting nanowire single photon detectors during a photo detection event, is modeled by a special electrical circuits (two circuit). Finally, current through the wire is calculated by solving equations of models.

Keywords: NbN, nanowire meander, superconducting single photon detector, kinetic inductance.

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Authors: Z. X. Chen, N. Singh, D.-L. Kwong

Abstract:

This paper presents a vertical silicon nanowire n- MOSFET integrated with a CMOS-compatible fully-silicided (FUSI) NiSi2 gate. Devices with nanowire diameter of 50nm show good electrical performance (SS < 70mV/dec, DIBL < 30mV/V, Ion/Ioff > 107). Most significantly, threshold voltage tunability of about 0.2V is shown. Although threshold voltage remains low for the 50nm diameter device, it is expected to become more positive as nanowire diameter reduces.

Keywords: NiSi , fully-silicided (FUSI) gate, vertical siliconnanowire (SiNW), CMOS compatible.

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Authors: Ajay Kushwaha, Hemen Kalita, M. Aslam

Abstract:

Post growth annealing of solution grown ZnO nanowire array is performed under controlled oxygen ambience. The role of annealing over surface defects and their consequence on dark/photo-conductivity and photosensitivity of nanowire array is investigated. Surface defect properties are explored using various measurement tools such as contact angle, photoluminescence, Raman spectroscopy and XPS measurements. The contact angle of the NW films reduces due to oxygen annealing and nanowire film surface changes from hydrophobic (96°) to hydrophilic (16°). Raman and XPS spectroscopy reveal that oxygen annealing improves the crystal quality of the nanowire films. The defect band emission intensity (relative to band edge emission, ID/IUV) reduces from 1.3 to 0.2 after annealing at 600 °C at 10 SCCM flow of oxygen. An order enhancement in dark conductivity is observed in O2 annealed samples, while photoconductivity is found to be slightly reduced due to lower concentration of surface related oxygen defects.

Keywords: Zinc Oxide, Surface defects, Photoluminescence, Photoconductivity, Photosensor and Nanowire thin film.

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Authors: N. Shen, Z. X. Chen, K.D. Buddharaju, H. M. Chua, X. Li, N. Singh, G.Q Lo, D.-L. Kwong

Abstract:

In this paper, we present a vertical wire NMOS device fabricated using CMOS compatible processes. The impact of temperature on various device parameters is investigated in view of usual increase in surrounding temperature with device density.

Keywords: Gate-all-around, temperature dependence, silicon nanowire

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Authors: Y. Li, K. Buddharaju, N. Singh, G. Q. Lo, S. J. Lee

Abstract:

Silicon nanowire (SiNW) based thermoelectric device (TED) has potential applications in areas such as chip level cooling/ energy harvesting. It is a great challenge however, to assemble an efficient device with these SiNW. The presence of parasitic in the form of interfacial electrical resistance will have a significant impact on the performance of the TED. In this work, we explore the effect of the electrical contact resistance on the performance of a TED. Numerical simulations are performed on SiNW to investigate such effects on its cooling performance. Intrinsically, SiNW individually without the unwanted parasitic effect has excellent cooling power density. However, the cooling effect is undermined with the contribution of the electrical contact resistance.

Keywords: Thermoelectric, silicon, nanowire, electrical contact resistance, parasitics.

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Authors: Fatemeh Karimi, Morteza Fathipour, Hamdam Ghanatian, Vala Fathipour

Abstract:

In this paper electrical characteristics of various kinds of multiple-gate silicon nanowire transistors (SNWT) with the channel length equal to 7 nm are compared. A fully ballistic quantum mechanical transport approach based on NEGF was employed to analyses electrical characteristics of rectangular and cylindrical silicon nanowire transistors as well as a Double gate MOS FET. A double gate, triple gate, and gate all around nano wires were studied to investigate the impact of increasing the number of gates on the control of the short channel effect which is important in nanoscale devices. Also in the case of triple gate rectangular SNWT inserting extra gates on the bottom of device can improve the application of device. The results indicate that by using gate all around structures short channel effects such as DIBL, subthreshold swing and delay reduces.

Keywords: SNWT (silicon nanowire transistor), non equilibriumGreen's function (NEGF), double gate (DG), triple gate (TG), multiple gate, cylindrical nano wire (CW), rectangular nano wire(RW), Poisson_ Schrödinger solver, drain induced barrier lowering(DIBL).

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Authors: Y. Li, K. Buddharaju, X. P. Wang

Abstract:

The mechanism of nickel (Ni) metallization in silicon-germanium (Si_0.5Ge_0.5) alloy nanowire (NW) was studied. Transmission electron microscope imaging with in-situ annealing was conducted at temperatures of 200^oC to 600°C. During rapid formation of Ni germanosilicide, loss of material from from the SiGe NW occurred which led to the formation of a thin Ni germanosilicide filament and eventual void. Energy dispersive X-ray spectroscopy analysis along the SiGe NW before and after annealing determined that Ge atoms tend to out-diffuse from the Ni germanosilicide towards the Ni source in the course of annealing. A model for the Ni germanosilicide formation in SiGe NW is proposed to explain this observation.

Keywords: SiGe, nanowires, germanosilicide.

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Authors: Fatemeh Karimi, Morteza Fathipour, Hamdam Ghanatian, Vala Fathipour

Abstract:

In this paper we investigate the electrical characteristics of a new structure of gate all around strained silicon nanowire field effect transistors (FETs) with dual dielectrics by changing the radius (RSiGe) of silicon-germanium (SiGe) wire and gate dielectric. Indeed the effect of high-κ dielectric on Field Induced Barrier Lowering (FIBL) has been studied. Due to the higher electron mobility in tensile strained silicon, the n-type FETs with strained silicon channel have better drain current compare with the pure Si one. In this structure gate dielectric divided in two parts, we have used high-κ dielectric near the source and low-κ dielectric near the drain to reduce the short channel effects. By this structure short channel effects such as FIBL will be reduced indeed by increasing the RSiGe, ID-VD characteristics will be improved. The leakage current and transfer characteristics, the threshold-voltage (Vt), the drain induced barrier height lowering (DIBL), are estimated with respect to, gate bias (VG), RSiGe and different gate dielectrics. For short channel effects, such as DIBL, gate all around strained silicon nanowire FET have similar characteristics with the pure Si one while dual dielectrics can improve short channel effects in this structure.

Keywords: SNWT (silicon nanowire transistor), Tensile Strain, high-κ dielectric, Field Induced Barrier Lowering (FIBL), cylindricalnano wire (CW), drain induced barrier lowering (DIBL).

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Authors: Stepan Petrosyan, Ashkhen Yesayan, Suren Nersesyan

Abstract:

We have developed an analytic model for the radial pn-junction in a nanowire (NW) core-shell structure utilizing as a new building block in different semiconductor devices. The potential distribution through the p-n-junction is calculated and the analytical expressions are derived to compute the depletion region widths. We show that the widths of space charge layers, surrounding the core, are the functions of core radius, which is the manifestation of so called classical size effect. The relationship between the depletion layer width and the built-in potential in the asymptotes of infinitely large core radius transforms to square-root dependence specific for conventional planar p-n-junctions. The explicit equation is derived to compute the capacitance of radial p-n-junction. The current-voltage behavior is also carefully determined taking into account the “short base" effects.

Keywords: Snanowire, p-n- junction, barrier capacitance, high injection.

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Authors: Jyoti Narayan, S. Choudhary

Abstract:

Nanowire arrays of copper with uniform diameters have been synthesized by potentiostatic electrochemical metal deposition (EMD) of copper sulphate and potassium chloride solution within the nano-channels of porous Indium-Tin Oxide (ITO), also known as Tin doped Indium Oxide templates. The nanowires developed were fairly continuous with diameters ranging from 110-140 nm along the entire length. Single as well as poly-crystalline copper wires have been prepared by application of appropriate potential during the EMD process. Scanning electron microscopy (SEM), high resolution transmission electron microscopy (HRTEM), small angle electron diffraction (SAED) and atomic force microscopy (AFM) were used to characterize the synthesized nano wires at room temperature. The electrochemical response of synthesized products was evaluated by cyclic voltammetry while surface energy analysis was carried out using a Goniometer.

Keywords: Electro-deposition, Metallic nano-wires, Nanomaterials, Template synthesis

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Authors: Sang Hoon Lee, Tae Il Lee, Su Jeong Lee, Jae Min Myoung

Abstract:

In order to manufacture short gap single Si nanowire (NW) field effect transistor (FET) by imprinting and transferring method, we introduce the method using Al2O3 sacrificial layer. The diameters of cylindrical Si NW addressed between Au electrodes by dielectrophoretic (DEP) alignment method are controlled to 106, 128, and 148 nm. After imprinting and transfer process, cylindrical Si NW is embedded in PVP adhesive and dielectric layer. By curing transferred cylindrical Si NW and Au electrodes on PVP-coated p++ Si substrate with 200nm-thick SiO2, 3μm gap Si NW FET fabrication was completed. As the diameter of embedded Si NW increases, the mobility of FET increases from 80.51 to 121.24 cm2/V·s and the threshold voltage moves from –7.17 to –2.44 V because the ratio of surface to volume gets reduced.

Keywords: Al2O3 Sacrificial transfer layer, cylindrical silicon nanowires, Dielectrophorestic alignment, Field effect transistor.

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Authors: Emanuela Paranhos Lima, Vitaly Félix Rodríguez Esquerre

Abstract:

In this work, efficient directional coupler composed of dielectric waveguides and metallic film has been analyzed in details by simulations using finite element method (FEM). The structure consists of a step-index fiber with dielectric core, silica cladding, and a metal nanowire parallel to the core. The results show that an efficient conversion of optical dielectric modes to long range plasmonic is possible. Low insertion losses in conjunction with short coupling length and a broadband operation can be achieved under certain conditions. This kind of couplers has potential applications for the design of photonic integrated circuits for signal routing between dielectric/plasmonic waveguides, sensing, lithography, and optical storage systems. A high efficient focusing of light in a very small region can be obtained.

Keywords: Directional coupler, finite element method, metallic nanowire, plasmonic, surface plasmon polariton.

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Authors: Farid Jamali Sheini, Dilip S. Joag, Mahendra A. More

Abstract:

A simple approach is demonstrated for growing large scale, nearly vertically aligned ZnO nanowire arrays by thermal oxidation method. To reveal effect of temperature on growth and physical properties of the ZnO nanowires, gold coated zinc substrates were annealed at 300 °C and 400 °C for 4 hours duration in air. Xray diffraction patterns of annealed samples indicated a set of well defined diffraction peaks, indexed to the wurtzite hexagonal phase of ZnO. The scanning electron microscopy studies show formation of ZnO nanowires having length of several microns and average of diameter less than 500 nm. It is found that the areal density of wires is relatively higher, when the annealing is carried out at higher temperature i.e. at 400°C. From the field emission studies, the values of the turn-on and threshold field, required to draw emission current density of 10 μA/cm2 and 100 μA/cm2 are observed to be 1.2 V/μm and 1.7 V/μm for the samples annealed at 300 °C and 2.9 V/μm and 3.7 V/μm for that annealed at 400 °C, respectively. The field emission current stability, investigated over duration of more than 2 hours at the preset value of 1 μA, is found to be fairly good in both cases. The simplicity of the synthesis route coupled with the promising field emission properties offer unprecedented advantage for the use of ZnO field emitters for high current density applications.

Keywords: ZnO, Nanowires, Thermal oxidation, FieldEmission.

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Authors: Gul Afreen, Sreedevi Upadhyayula, Mahendra K. Sunkara

Abstract:

One-dimensional (1D) nanostructures like nanowires, nanotubes, and nanorods find variety of practical application owing to their unique physico-chemical properties. In this work, TiO₂ nanowires were synthesized by direct oxidation of titanium particles in a unique microwave plasma jet reactor. The prepared TiO₂ nanowires manifested the flexible features, and were characterized by using X-ray diffraction, Brunauer-Emmett-Teller (BET) surface area analyzer, UV-Visible and FTIR spectrophotometers, Scanning electron microscope, and Transmission electron microscope. Further, the photodegradation efficiency of these nanowires were tested against toxic organic dye like methylene blue (MB) and the results were compared with the commercial TiO₂. It was found that TiO₂ nanowires exhibited superior photocatalytic performance (89%) as compared to commercial TiO₂ (75%) after 60 min of reaction. This is attributed to the lower recombination rate and increased interfacial charge transfer in TiO₂ nanowire. Pseudo-first order kinetic modelling performed with the experimental results revealed that the rate constant of photodegradation in case of TiO₂ nanowire was 1.3 times higher than that of commercial TiO₂. Superoxide radical (O₂˙⁻) was found to be the major contributor in the photodegradation mechanism. Based on the trapping experiments, a plausible mechanism of the photocatalytic reaction is discussed.

Keywords: Heterogeneous catalysis, photodegradation, reactive oxygen species, TiO2 nanowires.

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Authors: Sunil Dehipawala, Gayathrie Amarasuriya, N. Gadura, G. Tremberger Jr, D. Lieberman, Harry Gafney, Todd Holden, T. Cheung

Abstract:

The iron environment in Fe-doped Vycor Anode was investigated with EXAFS using Brookhaven Synchrotron Light Source. The iron-reducing Shewanella oneidensis culture was grown in a microbial fuel cell under anaerobic respiration. The Fe bond length was found to decrease and correlate with the amount of biofilm growth on the Fe-doped Vycor Anode. The data suggests that Fe-doped Vycor Anode would be a good substrate to study the Shewanella oneidensis nanowire structure using EXAFS.

Keywords: EXAFS, Fourier Transform, Microbial Fuel Cell, Shewanella oneidensis.

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Authors: T. Hashimoto, N. Miki, H. Maki

Abstract:

We report the size dependence of 1D superconductivity in ultrathin (10-130 nm) nanowires produced by coating suspended carbon nanotubes with a superconducting NbN thin film. The resistance-temperature characteristic curves for samples with ≧25 nm wire width show the superconducting transition. On the other hand, for the samples with 10-nm width, the superconducting transition is not exhibited owing to the quantum size effect. The differential resistance vs. current density characteristic curves show some peak, indicating that Josephson junctions are formed in nanowires. The presence of the Josephson junctions is well explained by the measurement of the magnetic field dependence of the critical current. These understanding allow for the further expansion of the potential application of NbN, which is utilized for single photon detectors and so on.

Keywords: NbN nanowire, carbon nanotube, quantum size effect, Josephson junction

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Authors: Nikhil Jain, Yang Xu, Bin Yu

Abstract:

The material behavior of graphene, a single layer of carbon lattice, is extremely sensitive to its dielectric environment. We demonstrate improvement in electronic performance of graphene nanowire interconnects with full encapsulation by lattice-matching, chemically inert, 2D layered insulator hexagonal boron nitride (h- BN). A novel layer-based transfer technique is developed to construct the h-BN/MLG/h-BN heterostructures. The encapsulated graphene wires are characterized and compared with that on SiO2 or h-BN substrate without passivating h-BN layer. Significant improvements in maximum current-carrying density, breakdown threshold, and power density in encapsulated graphene wires are observed. These critical improvements are achieved without compromising the carrier transport characteristics in graphene. Furthermore, graphene wires exhibit electrical behavior less insensitive to ambient conditions, as compared with the non-passivated ones. Overall, h-BN/graphene/h- BN heterostructure presents a robust material platform towards the implementation of high-speed carbon-based interconnects.

Keywords: Two-dimensional nanosheet, graphene, hexagonal boron nitride, heterostructure, interconnects.

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Authors: Yong Pan, Li Wang, Xue Qiong Su, Dong Wen Gao

Abstract:

To date, nanomaterials have received extensive attention over the years because of their wide application. Various nanomaterials such as nanoparticles, nanowire, nanoring, nanostars and other nanostructures have begun to be systematically studied. The preparation of these materials by chemical methods is not only costly, but also has a long cycle and high toxicity. At the same time, preparation of nanoparticles of multi-doped composites has been limited due to the special structure of the materials. In order to prepare multi-doped composites with the same structure as macro-materials and simplify the preparation method, the Ga_xCo_1-xZnSe_0.4 (x = 0.1, 0.3, 0.5) nanoparticles are prepared by Pulse Laser Ablation (PLA) method. The particle component and structure are systematically investigated by X-ray diffraction (XRD) and Raman spectra, which show that the success of our preparation and the same concentration between nanoparticles (NPs) and target. Morphology of the NPs characterized by Transmission Electron Microscopy (TEM) indicates the circular-shaped particles in preparation. Fluorescence properties are reflected by PL spectra, which demonstrate the best performance in concentration of Ga_0.3Co_0.3ZnSe_0.4. Therefore, all the results suggest that PLA is promising to prepare the multi-NPs since it can modulate performance of NPs.

Keywords: PLA, physics, nanoparticles, multi-doped.

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Authors: Beibei Han, Yong-Jin Yoon, Muhammad Hamidullah, Angel Tsu-Hui Lin, Woo-Tae Park

Abstract:

This paper presents the design of a ring-shaped tri-axial fore sensor that can be incorporated into the tip of a guidewire for use in minimally invasive surgery (MIS). The designed sensor comprises a ring-shaped structure located at the center of four cantilever beams. The ringdesign allows surgical tools to be easily passed through which largely simplified the integration process. Silicon nanowires (SiNWs) are used aspiezoresistive sensing elementsembeddedon the four cantilevers of the sensor to detect the resistance change caused by the applied load.An integration scheme with new designed guidewire tip structure having two coils at the distal end is presented. Finite element modeling has been employed in the sensor design to find the maximum stress location in order to put the SiNWs at the high stress regions to obtain maximum output. A maximum applicable force of 5 mN is found from modeling. The interaction mechanism between the designed sensor and a steel wire has been modeled by FEM. A linear relationship between the applied load on the steel wire and the induced stress on the SiNWs were observed.

Keywords: Triaxial MEMS force sensor, Ring shape, Silicon Nanowire, Minimally invasive surgery.

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