{"title":"Fabrication and Characterization of Poly-Si Vertical Nanowire Thin Film Transistor","authors":"N. Shen, T. T. Le, H. Y. Yu, Z. X. Chen, K. T. Win, N. Singh, G. Q. Lo, D. -L. Kwong","volume":57,"journal":"International Journal of Materials and Metallurgical Engineering","pagesStart":798,"pagesEnd":801,"ISSN":"1307-6892","URL":"https:\/\/publications.waset.org\/pdf\/4635","abstract":"
In this paper, we present a vertical nanowire thin film transistor with gate-all-around architecture, fabricated using CMOS compatible processes. A novel method of fabricating polysilicon vertical nanowires of diameter as small as 30 nm using wet-etch is presented. Both n-type and p-type vertical poly-silicon nanowire transistors exhibit superior electrical characteristics as compared to planar devices. On a poly-crystalline nanowire of 30 nm diameter, high Ion\/Ioff ratio of 106, low drain-induced barrier lowering (DIBL) of 50 mV\/V, and low sub-threshold slope SS~100mV\/dec are demonstrated for a device with channel length of 100 nm.<\/p>\r\n","references":"[1] T. Uchida, \"Present and future trend of electron device technology in flat panel display,\" in IEDM Tech. Dig., Dec. 1991, pp. 5-10.\r\n[2] M. Kimura, I. Yudasaka, S. Kanbe, H. Kobayashi, H. Kiguchi, S. Seki, S. Miyashita, T. Shimoda, T. Ozawa, K. Kitawada, T. Nakazawa, W. Miyazawa and H. Ohshima, \"Low-temperature poly-silicon thin-film transistor driving with integrated driver for high-resolution light emitting polymer display,\" IEEE Trans. Electron Devices., vol. 46, no. 12, pp. 2282-2288, Dec. 1999.\r\n[3] K. Chung, M.P. Hong, C.W. Kim, I. Kang, \"Needs and solutions of future flat panel display for information technology industry,\" in IEDM Tech. Dig., Dec. 2002, pp. 385-388.\r\n[4] S.J. Lee, S.W. Lee, K.M. Oh, S.J. Park, K.E. Lee, Y.S. Yoo, K.M. Lim, M.S. Yang, Y.S. Yang and Y.K. Hwang, \"A Novel Five-Photomask Low-Temperature Polycrystalline Silicon CMOS Structure for AMLCD Application,\" IEEE Trans. Electron Devices., vol. 57, no. 9, pp. 2324\u00ac2329, Sep. 2010.\r\n[5] O.A. Adan, K. Suzuki, H. Shibayama, and R. Miyake, \"A half-micron SRAM cell using a double-gated self-aligned polysilicon pMOS thin film transistor (TFT) load,\" in VLSI Symp. Tech. Dig., 1990, pp. 19-20. \r\n[6] C.M. Lee and B.Y. Tsui, \"A High-Performance 30-nm Gate-All-Around Poly-Si Nanowire Thin-Film Transistor With NH3 Plasma Treatment,\" IEEE Electron Device Lett., vol. 31, no. 7, pp. 683-685, Jul. 2010.\r\n[7] H. Sakuraba, K. Kinoshita, T. Tanigami, T. Yokoyama, S. horii, M. Saitoh, K. Sakiyama, T. Endoh, and F. Masuoka, \"New Three-Dimensional High-Density Stacked-Surrounding Gate Transistor (S-SGT) Flash Memory Architecture Using Self-Aligned Interconnection Fabrication Technology without Photolithography Process for Tera-Bits and Beyond,\" Jpn. J. Appl. Phys., vol. 43, no. 4B, pp. 2217-2219, 2004.\r\n[8] N. Singh, A. Agarwal, L.K. Bera, T.Y. Liow, R. Yang, S.C. Rustagi, C.H. Tung, R. Kumar, G.Q. Lo, N. Balasubramanian, and D.-L. Kwong, \"High-Performance Fully Depleted Silicon Nanowire (Diameter 5 nm) Gate-All-Around CMOS Devices,\" IEEE Electron Device Lett., vol. 27, no. 5, pp. 383-386, May. 2006.\r\n[9] B. Yang, K.D. Buddharaju, S.H.G. Teo, N. Singh, G.Q. Lo, N. and D.-\r\nL. Kwong, \"Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET,\" IEEE Electron Device Lett., vol. 29, no. 7, pp. 791-794, Jul. 2008.","publisher":"World Academy of Science, Engineering and Technology","index":"Open Science Index 57, 2011"}