A Novel Four-Transistor SRAM Cell with Low Dynamic Power Consumption

Authors: Arash Azizi Mazreah, Mohammad T. Manzuri Shalmani, Hamid Barati, Ali Barati

Abstract:

This paper presents a novel CMOS four-transistor SRAM cell for very high density and low power embedded SRAM applications as well as for stand-alone SRAM applications. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 20% smaller than a conventional six-transistor cell using same design rules. Also proposed cell uses two word-lines and one pair bit-line. Read operation perform from one side of cell, and write operation perform from another side of cell, and swing voltage reduced on word-lines thus dynamic power during read/write operation reduced. The fabrication process is fully compatible with high-performance CMOS logic technologies, because there is no need to integrate a poly-Si resistor or a TFT load. HSPICE simulation in standard 0.25μm CMOS technology confirms all results obtained from this paper.

Keywords: Positive feedback, leakage current, read operation, write operation, dynamic energy consumption.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1334317

References:

[1] K. Osada, Y. Saitoh, E. Ibe, and K. Ishibashi, "16.7-fA/cell tunnelleakage- suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors," IEEE J. Solid-State Circuits, vol. 38, no. 11, Nov. 2003, pp. 1952-1957.
[2] Fdf M. Yamaoka, Y. Shinozaki, N. Maeda, Y. Shimazaki, K. Kato, S. Shimada, K. Yanagisawa, and K. Osada, "A 300-MHz, 25 ╬╝A /Mbitleakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2004, pp. 494-495.
[3] K. Ishibashi, K. Takasugi, K. Komiyaji, H. Toyoshima, T. Yamanaka, A. Fukami, N. Hashimoto, N. Ohki, A. Shimizu, T. Hashimoto, T. Nagano, and T. Nishida, "A 6-ns 4-Mb CMOS SRAM with offset-voltageinsensitive current sense amplifiers," IEEE J. Solid-State Circuits, vol. 30, no. 4, Apr. 1995, pp. 480-486.
[4] T. Yamanaka, T. Hashimoto, N. Hasegawa, T. Tanaka, N. Hashimoto, A. Shimizu, N. Ohki, K. Ishibashi, K. Sasaki, T. Nishida, T. Mine, E. Takeda, and T. Nagano, "Advanced TFT SRAM cell technology using a phase-shift lithography," IEEE Trans. Electron. Devices, vol. 42, no. 7, Jul. 1995, pp. 1305-1313.
[5] A. Kotabe, K. Osada, N. Kitai, M. Fujioka, S. Kamohara, M. Moniwa, S. Morita, and Y. Saitoh, "A Low-Power Four-Transistor SRAM Cell With a Stacked Vertical Poly-Silicon PMOS and a Dual-Word-Voltage Scheme," IEEE J. Solid-State Circuits, vol. 40, no. 4, April 2005, pp. 870-876.
[6] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd ed., Prentice Hall, 2002. pp. 209- 211.
[7] K. Martin, Digital Integrated Circuit Design, Oxford university press: New York, 2000. pp. 443-448.
[8] K. Noda, K. Matsui, K. Imai, K. Takeda, and N. Nakamura, "A loadless CMOS four-transistor SRAM cell in a 0.18- logic technology," IEEE Trans. Electron. Devices, vol. 48, no. 12, Dec. 2001, pp. 2851-2855.