Search results for: CMOS
174 A 1.8 V RF CMOS Active Inductor with 0.18 um CMOS Technology
Authors: Siavash Heydarzadeh, Massoud Dousti
A active inductor in CMOS techonology with a supply voltage of 1.8V is presented. The value of the inductance L can be in the range from 0.12nH to 0.25nH in high frequency(HF). The proposed active inductor is designed in TSMC 0.18-um CMOS technology. The power dissipation of this inductor can retain constant at all operating frequency bands and consume around 20mW from 1.8V power supply. Inductors designed by integrated circuit occupy much smaller area, for this reason,attracted researchers attention for more than decade. In this design we used Advanced Designed System (ADS) for simulating cicuit.
Keywords: CMOS active inductor , 0.18um CMOS technology , ADSProcedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 3223
173 High Speed and Ultra Low-voltage CMOS NAND and NOR Domino Gates
Authors: Yngvar Berg, Omid Mirmotahari
In this paper we ultra low-voltage and high speed CMOS domino logic. For supply voltages below 500mV the delay for a ultra low-voltage NAND2 gate is aproximately 10% of a complementary CMOS inverter. Furthermore, the delay variations due to mismatch is much less than for conventional CMOS. Differential domino gates for AND/NAND and OR/NOR operation are presented.
Keywords: Low-voltage, high-speed, NAND, NOR, CMOS.Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2422
172 Design of a CMOS Differential Operational Transresistance Amplifier in 90 nm CMOS Technology
Authors: Hafiz Muhammad Obaid, Umais Tayyab, Shabbir Majeed Ch.
In this paper, a CMOS differential operational transresistance amplifier (OTRA) is presented. The amplifier is designed and implemented in a standard umc90-nm CMOS technology. The differential OTRA provides wider bandwidth at high gain. It also shows much better rise and fall time and exhibits a very good input current dynamic range of 50 to 50 μA. The OTRA can be used in many analog VLSI applications. The presented amplifier has high gain bandwidth product of 617.6 THz Ω. The total power dissipation of the presented amplifier is also very low and it is 0.21 mW.
Keywords: CMOS, differential, operational transresistance amplifier, OTRA, 90 nm, VLSI.Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 944
171 Algorithm Design and Performance Evaluation of Equivalent CMOS Model
Authors: Parvinder S. Sandhu, Iqbaldeep Kaur, Amit Verma, Inderpreet Kaur, Birinderjit S. Kalyan
Abstract:This work is a proposed model of CMOS for which the algorithm has been created and then the performance evaluation of this proposition has been done. In this context, another commonly used model called ZSTT (Zero Switching Time Transient) model is chosen to compare all the vital features and the results for the Proposed Equivalent CMOS are promising. In the end, the excerpts of the created algorithm are also included
Keywords: Dual Capacitor Model, ZSTT, CMOS, SPICEMacro-Model.Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1197
170 LFSR Counter Implementation in CMOS VLSI
Authors: Doshi N. A., Dhobale S. B., Kakade S. R.
Abstract:As chip manufacturing technology is suddenly on the threshold of major evaluation, which shrinks chip in size and performance, LFSR (Linear Feedback Shift Register) is implemented in layout level which develops the low power consumption chip, using recent CMOS, sub-micrometer layout tools. Thus LFSR counter can be a new trend setter in cryptography and is also beneficial as compared to GRAY & BINARY counter and variety of other applications. This paper compares 3 architectures in terms of the hardware implementation, CMOS layout and power consumption, using Microwind CMOS layout tool. Thus it provides solution to a low power architecture implementation of LFSR in CMOS VLSI.
Keywords: Chip technology, Layout level, LFSR, Pass transistorProcedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 4413
169 The Design of PFM Mode DC-DC Converter with DT-CMOS Switch
Authors: Jae-Chang Kwak, Yong-Seo Koo
The high efficiency power management IC (PMIC) with switching device is presented in this paper. PMIC is controlled with PFM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS (DT-CMOS) with low on-resistance is designed to decrease conduction loss. The threshold voltage of DT-CMOS drops as the gate voltage increase, resulting in a much higher current handling capability than standard MOSFET. PFM control circuits consist of a generator, AND gate and comparator. The generator is made to have 1.2MHz oscillation voltage. The DC-DC converter based on PFM control circuit and low on-resistance switching device is presented in this paper.
Keywords: DT-CMOS, PMIC, PFM, DC-DC converter.Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 3055
168 Design of CMOS CFOA Based on Pseudo Operational Transconductance Amplifier
Authors: Hassan Jassim Motlak
A novel design technique employing CMOS Current Feedback Operational Amplifier (CFOA) is presented. The feature of consumption very low power in designing pseudo-OTA is used to decreasing the total power consumption of the proposed CFOA. This design approach applies pseudo-OTA as input stage cascaded with buffer stage. Moreover, the DC input offset voltage and harmonic distortion (HD) of the proposed CFOA are very low values compared with the conventional CMOS CFOA due to the symmetrical input stage. P-Spice simulation results are obtained using 0.18μm MIETEC CMOS process parameters and supply voltage of ±1.2V, 50μA biasing current. The p-spice simulation shows excellent improvement of the proposed CFOA over existing CMOS CFOA. Some of these performance parameters, for example, are DC gain of 62. dB, openloop gain bandwidth product of 108 MHz, slew rate (SR+) of +71.2V/μS, THD of -63dB and DC consumption power (PC) of 2mW.
Keywords: Pseudo-OTA used CMOS CFOA, low power CFOA, high-performance CFOA, novel CFOA.Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2586
167 CMOS-Compatible Deposited Materials for Photonic Layers Integrated above Electronic Integrated Circuit
Authors: Shiyang Zhu, G. Q. Lo, D. L. Kwong
Silicon photonics has generated an increasing interest in recent years mainly for optical communications optical interconnects in microelectronic circuits or bio-sensing applications. The development of elementary passive and active components (including detectors and modulators), which are mainly fabricated on the silicon on insulator platform for CMOS-compatible fabrication, has reached such a performance level that the integration challenge of silicon photonics with microelectronic circuits should be addressed. Since crystalline silicon can only be grown from another silicon crystal, making it impossible to deposit in this state, the optical devices are typically limited to a single layer. An alternative approach is to integrate a photonic layer above the CMOS chip using back-end CMOS fabrication process. In this paper, various materials, including silicon nitride, amorphous silicon, and polycrystalline silicon, for this purpose are addressed.
Keywords: Silicon photonics, CMOS, Integration.Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2352
166 Design of an Ultra Low Power Low Phase Noise CMOS LC Oscillator
Authors: Mahdi Ebrahimzadeh
Abstract:In this paper we introduce an ultra low power CMOS LC oscillator and analyze a method to design a low power low phase noise complementary CMOS LC oscillator. A 1.8GHz oscillator is designed based on this analysis. The circuit has power supply equal to 1.1 V and dissipates 0.17 mW power. The oscillator is also optimized for low phase noise behavior. The oscillator phase noise is -126.2 dBc/Hz and -144.4 dBc/Hz at 1 MHz and 8 MHz offset respectively.
Keywords: LC oscillator, Low Power, Low Phase NoiseProcedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 3640
165 3.5-bit Stage of the CMOS Pipeline ADC
Authors: Gao Wei, Xu Minglu, Xu Yan, Zhang Xiaotong, Wang Xinghua
A 3.5-bit stage of the CMOS pipelined ADC is proposed. In this report, the main part of 3.5-bit stage ADC is introduced. How the MDAC, comparator and encoder worked and designed are shown in details. Besides, an OTA which is used in fully differential pipelined ADC was described. Using gain-boost architecture with differential amplifier, this OTA achieve high-gain and high-speed. This design was using CMOS 0.18um process and simulation in Cadence. The result of the simulation shows that the OTA has a gain up to 80dB, the unity gain bandwidth of about 1.138GHz with 2pF load.
Keywords: pipelined ADC, MDAC, operational amplifier.Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 3348
164 A Programmable FSK-Modulator in 350nm CMOS Technology
Authors: Nasir Mehmood, Saad Rahman, Vinodh Ravinath, Mahesh Balaji
Abstract:This paper describes the design of a programmable FSK-modulator based on VCO and its implementation in 0.35m CMOS process. The circuit is used to transmit digital data at 100Kbps rate in the frequency range of 400-600MHz. The design and operation of the modulator is discussed briefly. Further the characteristics of PLL, frequency synthesizer, VCO and the whole design are elaborated. The variation among the proposed and tested specifications is presented. Finally, the layout of sub-modules, pin configurations, final chip and test results are presented.
Keywords: FSK Modulator, CMOS, VCO, Phase Locked Loop, Frequency Synthesizer.Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1618
163 Temperature Sensor IC Design for Intracranial Monitoring Device
Authors: Wai Pan Chan, Minkyu Je
A precision CMOS chopping amplifier is adopted in this work to improve a CMOS temperature sensor high sensitive enough for intracranial temperature monitoring. An amplified temperature sensitivity of 18.8 ± 3*0.2 mV/oC is attained over the temperature range from 20 oC to 80 oC from a given 10 samples of the same wafer. The analog frontend design outputs the temperature dependent and the temperature independent signals which can be directly interfaced to a 10 bit ADC to accomplish an accurate temperature instrumentation system.
Keywords: Chopping, analog frontend, CMOS temperature sensor, traumatic brain injury (TBI), intracranial temperature monitoring.Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1840
162 A Low Power High Frequency CMOS RF Four Quadrant Analog Mixer
Authors: M. Aleshams, A. Shahsavandi
Abstract:This paper describes a CMOS four-quadrant multiplier intended for use in the front-end receiver by utilizing the square-law characteristic of the MOS transistor in the saturation region. The circuit is based on 0.35 um CMOS technology simulated using HSPICE software. The mixer has a third-order inter the power consumption is 271uW from a single 1.2V power supply. One of the features of the proposed design is using two MOS transistors limitation to reduce the supply voltage, which leads to reduce the power consumption. This technique provides a GHz bandwidth response and low power consumption.
Keywords: RF-Mixer, Multiplier, cut-off frequency, power consumptionProcedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1899
161 0.13-μm CMOS Vector Modulator for Wireless Backhaul System
Authors: J. S. Kim, N. P. Hong
In this paper, a CMOS vector modulator designed for wireless backhaul system based on 802.11ac is presented. A poly phase filter and sign select switches yield two orthogonal signal paths. Two variable gain amplifiers with strongly reduced phase shift of only ±5 ° are used to weight these paths. It has a phase control range of 360 ° and a gain range of -10 dB to 10 dB. The current drawn from a 1.2 V supply amounts 20.4 mA. Using a 0.13 mm technology, the chip die area amounts 1.47x0.75 mm².
Keywords: CMOS, vector modulator, backhaul, 802.11ac.Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2150
160 Inverter Based Gain-Boosting Fully Differential CMOS Amplifier
Authors: Alpana Agarwal, Akhil Sharma
This work presents a fully differential CMOS amplifier consisting of two self-biased gain boosted inverter stages, that provides an alternative to the power hungry operational amplifier. The self-biasing avoids the use of external biasing circuitry, thus reduces the die area, design efforts, and power consumption. In the present work, regulated cascode technique has been employed for gain boosting. The Miller compensation is also applied to enhance the phase margin. The circuit has been designed and simulated in 1.8 V 0.18 µm CMOS technology. The simulation results show a high DC gain of 100.7 dB, Unity-Gain Bandwidth of 107.8 MHz, and Phase Margin of 66.7o with a power dissipation of 286 μW and makes it suitable candidate for the high resolution pipelined ADCs.
Keywords: CMOS amplifier, gain boosting, inverter-based amplifier, self-biased inverter.Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2256
159 Designing of Full Adder Using Low Power Techniques
Authors: Shashank Gautam
This paper proposes techniques like MT CMOS, POWER GATING, DUAL STACK, GALEOR and LECTOR to reduce the leakage power. A Full Adder has been designed using these techniques and power dissipation is calculated and is compared with general CMOS logic of Full Adder. Simulation results show the validity of the proposed techniques is effective to save power dissipation and to increase the speed of operation of the circuits to a large extent.
Keywords: Low Power, MT CMOS, Galeor, Lector, Power Gating, Dual Stack, Full Adder.Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2015
158 Versatile Dual-Mode Class-AB Four-Quadrant Analog Multiplier
Authors: Montree Kumngern, Kobchai Dejhan
Abstract:Versatile dual-mode class-AB CMOS four-quadrant analog multiplier circuit is presented. The dual translinear loops and current mirrors are the basic building blocks in realization scheme. This technique provides; wide dynamic range, wide-bandwidth response and low power consumption. The major advantages of this approach are; its has single ended inputs; since its input is dual translinear loop operate in class-AB mode which make this multiplier configuration interesting for low-power applications; current multiplying, voltage multiplying, or current and voltage multiplying can be obtainable with balanced input. The simulation results of versatile analog multiplier demonstrate a linearity error of 1.2 %, a -3dB bandwidth of about 19MHz, a maximum power consumption of 0.46mW, and temperature compensated. Operation of versatile analog multiplier was also confirmed through an experiment using CMOS transistor array.
Keywords: Class-AB, dual-mode CMOS analog multiplier, CMOS analog integrated circuit, CMOS translinear integrated circuit.Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2136
157 High Speed NP-CMOS and Multi-Output Dynamic Full Adder Cells
Authors: Reza Faghih Mirzaee, Mohammad Hossein Moaiyeri, Keivan Navi
Abstract:In this paper we present two novel 1-bit full adder cells in dynamic logic style. NP-CMOS (Zipper) and Multi-Output structures are used to design the adder blocks. Characteristic of dynamic logic leads to higher speeds than the other standard static full adder cells. Using HSpice and 0.18┬Ám CMOS technology exhibits a significant decrease in the cell delay which can result in a considerable reduction in the power-delay product (PDP). The PDP of Multi-Output design at 1.8v power supply is around 0.15 femto joule that is 5% lower than conventional dynamic full adder cell and at least 21% lower than other static full adders.
Keywords: Bridge Style, Dynamic Logic, Full Adder, HighSpeed, Multi Output, NP-CMOS, Zipper.Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 3093
156 Design and Characterization of a CMOS Process Sensor Utilizing Vth Extractor Circuit
Authors: Rohana Musa, Yuzman Yusoff, Chia Chieu Yin, Hanif Che Lah
Abstract:This paper presents the design and characterization of a low power Complementary Metal Oxide Semiconductor (CMOS) process sensor. The design is targeted for implementation using Silterra’s 180 nm CMOS process technology. The proposed process sensor employs a voltage threshold (Vth) extractor architecture for detection of variations in the fabrication process. The process sensor generates output voltages in the range of 401 mV (fast-fast corner) to 443 mV (slow-slow corner) at nominal condition. The power dissipation for this process sensor is 6.3 µW with a supply voltage of 1.8V with a silicon area of 190 µm X 60 µm. The preliminary result of this process sensor that was fabricated indicates a close resemblance between test and simulated results.
Keywords: CMOS Process sensor, Process, Voltage and Temperature (PVT) sensor, threshold extractor circuit, Vth extractor circuit.Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 545
155 A Fault-Tolerant Full Adder in Double Pass CMOS Transistor
Authors: Abdelmonaem Ayachi, Belgacem Hamdi
This paper presents a fault-tolerant implementation for adder schemes using the dual duplication code. To prove the efficiency of the proposed method, the circuit is simulated in double pass transistor CMOS 32nm technology and some transient faults are voluntary injected in the Layout of the circuit. This fully differential implementation requires only 20 transistors which mean that the proposed design involves 28.57% saving in transistor count compared to standard CMOS technology.
Keywords: Semiconductors, digital electronics, double pass transistor technology, Full adder, fault tolerance.Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1971
154 High-Speed High-Gain CMOS OTA for SC Applications
Authors: M.Yousefi, A.Vatanjou, F.Nazeri
Abstract:A fast settling multipath CMOS OTA for high speed switched capacitor applications is presented here. With the basic topology similar to folded-cascode, bandwidth and DC gain of the OTA are enhanced by adding extra paths for signal from input to output. Designed circuit is simulated with HSPICE using level 49 parameters (BSIM 3v3) in 0.35mm standard CMOS technology. DC gain achieved is 56.7dB and Unity Gain Bandwidth (UGB) obtained is 1.15GHz. These results confirm that adding extra paths for signal can improve DC gain and UGB of folded-cascode significantly.
Keywords: OTA (Operational Transconductance Amplifier), DC gain, Unity Gain Bandwidth (UGBW)Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 3463
153 Real-Time Digital Oscilloscope Implementation in 90nm CMOS Technology FPGA
Authors: Nasir Mehmood, Jens Ogniewski, Vinodh Ravinath
Abstract:This paper describes the design of a real-time audiorange digital oscilloscope and its implementation in 90nm CMOS FPGA platform. The design consists of sample and hold circuits, A/D conversion, audio and video processing, on-chip RAM, clock generation and control logic. The design of internal blocks and modules in 90nm devices in an FPGA is elaborated. Also the key features and their implementation algorithms are presented. Finally, the timing waveforms and simulation results are put forward.
Keywords: CMOS, VLSI, Oscilloscope, Field Programmable Gate Array (FPGA), VHDL, Video Graphics Array (VGA)Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2990
152 Adaptive Sampling Algorithm for ANN-based Performance Modeling of Nano-scale CMOS Inverter
Authors: Dipankar Dhabak, Soumya Pandit
Abstract:This paper presents an adaptive technique for generation of data required for construction of artificial neural network-based performance model of nano-scale CMOS inverter circuit. The training data are generated from the samples through SPICE simulation. The proposed algorithm has been compared to standard progressive sampling algorithms like arithmetic sampling and geometric sampling. The advantages of the present approach over the others have been demonstrated. The ANN predicted results have been compared with actual SPICE results. A very good accuracy has been obtained.
Keywords: CMOS Inverter, Nano-scale, Adaptive Sampling, ArtificialNeural NetworkProcedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1521
151 Noise Optimization Techniques for 1V 1GHz CMOS Low-Noise Amplifiers Design
Authors: M. Zamin Khan, Yanjie Wang, R. Raut
A 1V, 1GHz low noise amplifier (LNA) has been designed and simulated using Spectre simulator in a standard TSMC 0.18um CMOS technology.With low power and noise optimization techniques, the amplifier provides a gain of 24 dB, a noise figure of only 1.2 dB, power dissipation of 14 mW from a 1 V power supply.Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2316
150 Integration of CMOS Biosensor into a Polymeric Lab-on-a-Chip System
Authors: T. Brettschneider, C. Dorrer, H. Suy, T. Braun, E. Jung, R. Hoofman, M. Bründel, R. Zengerle, F. Lärmer
We present an integration approach of a CMOS biosensor into a polymer based microfluidic environment suitable for mass production. It consists of a wafer-level-package for the silicon die and laser bonding process promoted by an intermediate hot melt foil to attach the sensor package to the microfluidic chip, without the need for dispensing of glues or underfiller. A very good condition of the sensing area was obtained after introducing a protection layer during packaging. A microfluidic flow cell was fabricated and shown to withstand pressures up to Δp = 780 kPa without leakage. The employed biosensors were electrically characterized in a dry environment.
Keywords: CMOS biosensor, laser bonding, silicon polymer integration, wafer level packaging.Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2916
149 Current Mode Logic Circuits for 10-bit 5GHz High Speed Digital to Analog Converter
Authors: Zhenguo Vincent Chia, Sheung Yan Simon Ng, Minkyu Je
This paper presents CMOS Current Mode Logic (CML) circuits for a high speed Digital to Analog Converter (DAC) using standard CMOS 65nm process. The CML circuits have the propagation delay advantage over its conventional CMOS counterparts due to smaller output voltage swing and tunable bias current. The CML circuits proposed in this paper can achieve a maximum propagation delay of only 9.3ps, which can satisfy the stringent requirement for the 5 GHz high speed DAC application. Another advantage for CML circuits is its dynamic symmetry characteristic resulting in a reduction of an additional inverter. Simulation results show that the proposed CML circuits can operate from 1.08V to 1.3V with temperature ranging from -40 to +120°C.
Keywords: Conventional, Current Mode Logic, DAC, DecoderProcedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 5700
148 Symbolic Analysis of Power Spectrum of CMOS Cross Couple Oscillator
Authors: Kittipong Tripetch
Abstract:This paper proposes for the first time symbolic formula of the power spectrum of CMOS Cross Couple Oscillator and its modified circuit. Many principles existed to derived power spectrum in microwave textbook such as impedance, admittance parameters, ABCD, H parameters, etc. It can be compared by graph of power spectrum which methodology is the best from the point of view of practical measurement setup such as condition of impedance parameter which used superposition of current to derived (its current injection at the other port of the circuit is zero, which is impossible in reality). Four graphs of impedance parameters of cross couple oscillator are proposed. After that four graphs of scattering parameters of CMOS cross coupled oscillator will be shown.
Keywords: Optimization, power spectrum, impedance parameter, scattering parameter.Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1442
147 A Novel Nano-Scaled SRAM Cell
Authors: Arash Azizi Mazreah, Mohammad Reza Sahebi, Mohammad T. Manzuri Shalmani
To help overcome limits to the density of conventional SRAMs and leakage current of SRAM cell in nanoscaled CMOS technology, we have developed a four-transistor SRAM cell. The newly developed CMOS four-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 19% smaller than a conventional six-transistor cell using same design rules. Also the leakage current of new cell is 60% smaller than a conventional sixtransistor SRAM cell. Simulation result in 65nm CMOS technology shows new cell has correct operation during read/write operation and idle mode.
Keywords: SRAM Cell, leakage current, cell area.Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1645
146 Design and Analysis of Low-Power, High Speed and Area Efficient 2-Bit Digital Magnitude Comparator in 90nm CMOS Technology Using Gate Diffusion Input
Authors: Fasil Endalamaw
Digital magnitude comparators based on Gate Diffusion Input (GDI) implementation technique are high speed and area-efficient, and they consume less power as compared to other implementation techniques. However, they are less efficient for some logic gates and have no full voltage swing. In this paper, we made a performance comparison between the GDI implementation technique and other implementation methods, such as Static CMOS, Pass Transistor Logic (PTL), and Transmission Gate (TG) in 90 nm, 120 nm, and 180 nm CMOS technologies using BSIM4 MOS model. We proposed a methodology (hybrid implementation) of implementing digital magnitude comparators which significantly improved the power, speed, area, and voltage swing requirements. Simulation results revealed that the hybrid implementation of digital magnitude comparators show a 10.84% (power dissipation), 41.6% (propagation delay), 47.95% (power-delay product (PDP)) improvement compared to the usual GDI implementation method. We used Microwind & Dsch Version 3.5 as well as the Tanner EDA 16.0 tools for simulation purposes.
Keywords: Efficient, gate diffusion input, high speed, low power, CMOS.Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 217
145 Variable Input Range Continuous-time Switched Current Delta-sigma Analog Digital Converter for RFID CMOS Biosensor Applications
Authors: Boram Kim, Shigeyasu Uno, Kazuo Nakazato
Continuous-time delta-sigma analog digital converter (ADC) for radio frequency identification (RFID) complementary metal oxide semiconductor (CMOS) biosensor has been reported. This delta-sigma ADC is suitable for digital conversion of biosensor signal because of small process variation, and variable input range. As the input range of continuous-time switched current delta-sigma ADC (Dynamic range : 50 dB) can be limited by using current reference, amplification of biosensor signal is unnecessary. The input range is switched to wide input range mode or narrow input range mode by command of current reference. When the narrow input range mode, the input range becomes ± 0.8 V. The measured power consumption is 5 mW and chip area is 0.31 mm^2 using 1.2 um standard CMOS process. Additionally, automatic input range detecting system is proposed because of RFID biosensor applications.
Keywords: continuous time, delta sigma, A/D converter, RFID, biosensor, CMOSProcedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1441