Ambipolar Effect Free Double Gate PN Diode Based Tunnel FET
In this paper, we present and investigate a double gate PN diode based tunnel field effect transistor (DGPNTFET). The importance of proposed structure is that the formation of different drain doping is not required and ambipolar effect in OFF state is completely removed for this structure. Validation of this structure to behave like a Tunnel Field Effect Transistor (TFET) is carried out through energy band diagrams and transfer characteristics. Simulated result shows point subthreshold slope (SS) of 19.14 mV/decade and ON to OFF current ratio (ION / IOFF) of 2.66 × 1014 (ION at VGS=1.5V, VDS=1V and IOFF at VGS=0V, VDS=1V) for gate length of 20nm and HfO2 as gate oxide at room temperature. Which indicate that the DGPNTFET is a promising candidate for nano-scale, ambipolar free switch.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1125423Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 594
 Coling JP, Baie X, Bayot V, Grivei E, “A silicon on-insulator quantum wire,” Solid State Electron, vol. 39, no. 1, pp.49-51, 1996.
 Colinge JP, “Multi-gate SOI MOSFETs,” Solid-State Electron. vol.48, no. 6, pp.897–905, Jun.2004.
 H.S.P. Wong, D.J. Frank, and P.M. Soloman, “Device design considerations for double gate, ground plane, and single gate ultrathin MOSFET’s at the 25nm channel length generation,” IEDM Tech Dig.1998, pp.407-410, 1998.
 K. Boucart and A. Ionescu, “Double gate tunnel FET with high-κ gate dielectric,” IEEE Trans. Electron Devices, vol. 54, no. 7, pp. 1725–1733, Jul. 2007.
 J. Appenzeller, Y.-M. Lin, J. Knoch, and P. Avouris, “Band-to-band tunneling in carbon nanotube field-effect transistors,” Phys. Rev. Lett., vol. 93, no. 19, pp. 196 805-1–196 805-4, Nov. 2004.
 J. Knoch, S. Mantl, and J. Appenzeller, “Impact of the dimensionality on the performance of tunneling FETs: Bulk versus one-dimensional devices,” Solid State Electron., vol. 51, no. 4, pp. 572–578, Apr. 2007.
 K. Gopalakrishnan, P. B. Griffin, and J. D. Plummer, “I-MOS: A novel semiconductor device with a subthreshold slope lower than kT/q,” in IEDM Tech. Dig., pp. 289–292, 2002.
 K. K. Bhuwalka, S. Sedlmaier, A. K. Ludsteck, C. Tolksdorf, J. Schulze, and I. Eisele, “Vertical tunnel field-effect transistor,” IEEE Trans. Electron Devices, vol. 51, no. 2, pp. 279–282, Feb. 2004.
 B. Ghosh and M. W. Akram, “Junctionless Tunnel Field Effect Transistor,” IEEE Electron Devices Letters, vol.34,no.5, pp. 584-586, May 2013.
 Samarth Agarwal, Gerhard Klimeek, and Mathieu Luisier, “Leakage-Reduction Design Concepts for Low-Power Vertical Tunneling Field-Effect Transistor,” IEEE Electron Device Letters, vol.31, no.6, pp. 621-623, June 2010.
 J.D. Querlioz, J.S. Martine, K. Huet, A. Bournel, V. Aubry-Fortuna, C. Chassat, S. Galdin,-Retailleau, and P. Dollfus, “On the ability of particle Monte Carlo technique to include quantum effects in nano-MOSFET simulation,” IEEE Trans. Electron Devices, vol. 54, no. 9, pp.2232-2242, Sep. 2007.
 Silvaco ATLAS, Device simulation software, 2012.
 V. K. Jain and A. Verma, “Ambipolar Behaviour of Tunnel Field Effect Transistor as an Advantage for Biosensing Applications,” Physics of semiconductor devices, Environmental Science and Engineering, vol.108, pp.171-174, Nov 2013.
 J. Koga and A. Toriumi, “Three-terminal silicon surface junction tunneling device for room temperature operation,” IEEE Electron Device Lett., vol. 20, no. 10, pp. 529–531, Oct. 1999.
 Dawait B. Abdi and M. Jagdesh Kumar, “Controlling ambipolar current in tunneling FETs using overlapping gate-on-drain,” Journal of the electron devices society, vol. 2, no.6, pp. 187-190, Nov. 2014.
 H. Nam, Min Hee Cho, Changhwan Shin, “ Symmetric tunnel field-effect transistor (S-TFET),” in Journal of Current Applied Physics, vol. 15, pp. 71-77, Nov 2014.