%0 Journal Article
	%A Shubhajit Roy Chowdhury and  Aritra Banerjee and  Aniruddha Roy and  Hiranmay Saha
	%D 2008
	%J International Journal of Electronics and Communication Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 22, 2008
	%T A high Speed 8 Transistor Full Adder Design Using Novel 3 Transistor XOR Gates
	%U https://publications.waset.org/pdf/1588
	%V 22
	%X The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three-transistor XOR gate and its performance has been investigated using 0.15um and 0.35um technologies. Compared to the earlier designed 10 transistor full adder, the proposed adder shows a significant improvement in silicon area and power delay product. The whole simulation has been carried out using HSPICE.

	%P 2244 - 2250