%0 Journal Article
	%A Xiang Li and  Zhixian Chen and  Zheng Fang and  Aashit Kamath and  Xinpeng Wang and  Navab Singh and  Guo-Qiang Lo and  Dim-Lee
Kwong
	%D 2012
	%J International Journal of Electronics and Communication Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 69, 2012
	%T Integration of Resistive Switching Memory Cell with Vertical Nanowire Transistor
	%U https://publications.waset.org/pdf/13780
	%V 69
	%X We integrate TiN/Ni/HfO2/Si RRAM cell with a
vertical gate-all-around (GAA) nanowire transistor to achieve
compact 4F2 footprint in a 1T1R configuration. The tip of the Si
nanowire (source of the transistor) serves as bottom electrode of the
memory cell. Fabricated devices with nanowire diameter ~ 50nm
demonstrate ultra-low current/power switching; unipolar switching
with 10μA/30μW SET and 20μA/30μW RESET and bipolar switching
with 20nA/85nW SET and 0.2nA/0.7nW RESET. Further, the
switching current is found to scale with nanowire diameter making the
architecture promising for future scaling.
	%P 918 - 920