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Simulation of High Performance Nanoscale Partially Depleted SOI n-MOSFET Transistors

Authors: Fatima Zohra Rahou, A. Guen Bouazza, B. Bouazza


Invention of transistor is the foundation of electronics industry. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been the key for the development of nanoelectronics technology. In the first part of this manuscript, we present a new generation of MOSFET transistors based on SOI (Silicon-On-Insulator) technology. It is a partially depleted Silicon-On-Insulator (PD SOI MOSFET) transistor simulated by using SILVACO software. This work was completed by the presentation of some results concerning the influence of parameters variation (channel length L and gate oxide thickness Tox) on our PDSOI n-MOSFET structure on its drain current and kink effect.

Keywords: SOI technology, PDSOI MOSFET, FDSOI MOSFET, Kink Effect, SILVACO TCAD.

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[1] D. Flandre, S. Adriaensen, A. Akheyar, A. Crahay, L. Demeˆus, P. Delatte, V. Dessard, B. Iniguez, A. N`eve, B. Katschmarskyj, P. Loumaye, J. Laconte, I. Martinez, G. Picun, E. Rauly, C. Renaux, D. Spˆote, M. Zitout, M. Dehan, B. Parvais, P. Simon, D Vanhoenacker, and JP. Raskin, “Fully-depleted SOI CMOS technology for heterogeneous micropower, high-temperature or RF microsystems,” Solid-State Electronics, vol. 45, pp. 541–549, February 2001.
[2] J.-O. Plouchart, N. Zamdmer, J. Kim, M. Sherony, Y. Tan, A. Ray, M. Talbi, L. F. Wagner, K. Wu, N.E. Lustig, S. Narasimha, P. O’Neil, N. Phan, M. Rohn, J. Strom, D. M. Friend, S. V. Kosonocky, D. R. Knebel, S. Kim, K. A. Jenkins, and M. M. Rivier, “Application of an SOI 0.12 μm CMOS technology to SoCs with low-power and high-frequency circuits,” IBM Journal of Research and Development, vol. 47, no. 5/6, pp. 611 – 629, September/November 2003.
[3] Jean-Pierre Colinge, Silicon-on-insulator technology: Materials To VLSI, Kluwer Academic Publisher, 1991.
[4] JP. Raskin, A. Viviani, D. Flandre, and JP. Colinge, Substrate crosstalk reduction using SOI technology, vol. 44, no. 12, pp. 2252–2261, December1997.
[5] Bertrand Parvais, thesis, Nonlinear Devices Characterization and Micromachining Techniques for RF Integrated Circuits, Université Catholique de Louvain, Louvain - la- Neuve, December 2004.
[6] FZ. Rahou, A. Guen-Bouazza, M. Rahou, Electrical Characteristics Comparison Between Fully-Depleted SOI MOSFET and Partially-Depleted SOIMOSFET using Silvaco Software ,Global Journal of Researches in Engineering, Volume 13 Issue 1 Version 1.0 Year 2013.
[7] Morin Dehan, Bertrand Parvais, Gilles Dambrine et Jean Pierre Raskin, Intérêts de la Technologie CMOS SOI pour les Applications Micro-ondes Faible Tension Faible Consommation, Université catholique de Louvain, Laboratoire d’Hyperfréquences - Place du Levant, 3,B-1348 Louvain-la-Neuve, Belgique, Email: [email protected], Institut d’Electronique et de Microélectronique du Nord (IEMN), Av. Poincaré, BP 69, F-59655 Villeneuve d’Ascq, France.
[8] Louis Harik, thesis, New Approach for SOI Pixel Sensor, Analysis and Implementation, Ecole Polytechnique Fédérale de Lausanne, Suisse, 2009.
[9] B. Cheng, V. Ramgopal Rao, and J.C.S. Woo, Sub 0.18 um SOI MOSFETs Using Lateral Asymmetric Channel Profile and Ge Pre-amorphization Salicide Technology, Proceedings of the IEEE SOI Conference, October 5-8, Stuart, Florida, USA, 1998.
[10] S. Cristoloveanu, and S.S. Li, Electrical Characterization of Silicon-On-Insulator Materials and Devices, Kluwer Academic Publishers, 1995.
[11] C.E.D. Chen, M. Matloubian, R. Sundaresan, B.Y. Mao, C.C. Wei, and G.P. Pollack, “Single Transistor Latch in SOI MOSFET’s,” IEEE Electron Device Lett., vol. 9, p. 636, 1988.
[12] Christophe PAVAGEAU, thèse, Utilisation des technologies CMOS SOI 130 nm pour des applications en gamme de fréquences millimétriques, Université de Sciences et Technologies de Lille 2005.