Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 1341

Search results for: Complementary Metal Oxide Semiconductor (CMOS)

1341 0.13-µm Complementary Metal-Oxide Semiconductor Vector Modulator for Beamforming System

Authors: J. S. Kim

Abstract:

This paper presents a 0.13-µm Complementary Metal-Oxide Semiconductor (CMOS) vector modulator for beamforming system. The vector modulator features a 360° phase and gain range of -10 dB to 10 dB with a root mean square phase and amplitude error of only 2.2° and 0.45 dB, respectively. These features make it a suitable for wireless backhaul system in the 5 GHz industrial, scientific, and medical (ISM) bands. It draws a current of 20.4 mA from a 1.2 V supply. The total chip size is 1.87x1.34 mm².

Keywords: CMOS, vector modulator, beamforming, wireless backhaul, ISM.

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1340 Design and Characterization of a CMOS Process Sensor Utilizing Vth Extractor Circuit

Authors: Rohana Musa, Yuzman Yusoff, Chia Chieu Yin, Hanif Che Lah

Abstract:

This paper presents the design and characterization of a low power Complementary Metal Oxide Semiconductor (CMOS) process sensor. The design is targeted for implementation using Silterra’s 180 nm CMOS process technology. The proposed process sensor employs a voltage threshold (Vth) extractor architecture for detection of variations in the fabrication process. The process sensor generates output voltages in the range of 401 mV (fast-fast corner) to 443 mV (slow-slow corner) at nominal condition. The power dissipation for this process sensor is 6.3 µW with a supply voltage of 1.8V with a silicon area of 190 µm X 60 µm. The preliminary result of this process sensor that was fabricated indicates a close resemblance between test and simulated results.

Keywords: CMOS Process sensor, Process, Voltage and Temperature (PVT) sensor, threshold extractor circuit, Vth extractor circuit.

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1339 Variable Input Range Continuous-time Switched Current Delta-sigma Analog Digital Converter for RFID CMOS Biosensor Applications

Authors: Boram Kim, Shigeyasu Uno, Kazuo Nakazato

Abstract:

Continuous-time delta-sigma analog digital converter (ADC) for radio frequency identification (RFID) complementary metal oxide semiconductor (CMOS) biosensor has been reported. This delta-sigma ADC is suitable for digital conversion of biosensor signal because of small process variation, and variable input range. As the input range of continuous-time switched current delta-sigma ADC (Dynamic range : 50 dB) can be limited by using current reference, amplification of biosensor signal is unnecessary. The input range is switched to wide input range mode or narrow input range mode by command of current reference. When the narrow input range mode, the input range becomes ± 0.8 V. The measured power consumption is 5 mW and chip area is 0.31 mm^2 using 1.2 um standard CMOS process. Additionally, automatic input range detecting system is proposed because of RFID biosensor applications.

Keywords: continuous time, delta sigma, A/D converter, RFID, biosensor, CMOS

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1338 High Speed and Ultra Low-voltage CMOS NAND and NOR Domino Gates

Authors: Yngvar Berg, Omid Mirmotahari

Abstract:

In this paper we ultra low-voltage and high speed CMOS domino logic. For supply voltages below 500mV the delay for a ultra low-voltage NAND2 gate is aproximately 10% of a complementary CMOS inverter. Furthermore, the delay variations due to mismatch is much less than for conventional CMOS. Differential domino gates for AND/NAND and OR/NOR operation are presented.

Keywords: Low-voltage, high-speed, NAND, NOR, CMOS.

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1337 Development of Manufacturing Simulation Model for Semiconductor Fabrication

Authors: Syahril Ridzuan Ab Rahim, Ibrahim Ahmad, Mohd Azizi Chik, Ahmad Zafir Md. Rejab, and U. Hashim

Abstract:

This research presents the development of simulation modeling for WIP management in semiconductor fabrication. Manufacturing simulation modeling is needed for productivity optimization analysis due to the complex process flows involved more than 35 percent re-entrance processing steps more than 15 times at same equipment. Furthermore, semiconductor fabrication required to produce high product mixed with total processing steps varies from 300 to 800 steps and cycle time between 30 to 70 days. Besides the complexity, expansive wafer cost that potentially impact the company profits margin once miss due date is another motivation to explore options to experiment any analysis using simulation modeling. In this paper, the simulation model is developed using existing commercial software platform AutoSched AP, with customized integration with Manufacturing Execution Systems (MES) and Advanced Productivity Family (APF) for data collections used to configure the model parameters and data source. Model parameters such as processing steps cycle time, equipment performance, handling time, efficiency of operator are collected through this customization. Once the parameters are validated, few customizations are made to ensure the prior model is executed. The accuracy for the simulation model is validated with the actual output per day for all equipments. The comparison analysis from result of the simulation model compared to actual for achieved 95 percent accuracy for 30 days. This model later was used to perform various what if analysis to understand impacts on cycle time and overall output. By using this simulation model, complex manufacturing environment like semiconductor fabrication (fab) now have alternative source of validation for any new requirements impact analysis.

Keywords: Advanced Productivity Family (APF), Complementary Metal Oxide Semiconductor (CMOS), Manufacturing Execution Systems (MES), Work In Progress (WIP).

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1336 CMOS Positive and Negative Resistors Based on Complementary Regulated Cascode Topology with Cross-Coupled Regulated Transistors

Authors: Kittipong Tripetch, Nobuhiko Nakano

Abstract:

Two types of floating active resistors based on a complementary regulated cascode topology with cross-coupled regulated transistors are presented in this paper. The first topology is a high swing complementary regulated cascode active resistor. The second topology is a complementary common gate with a regulated cross coupled transistor. The small-signal input resistances of the floating resistors are derived. Three graphs of the input current versus the input voltage for different aspect ratios are designed and plotted using the Cadence Spectre 0.18-µm Rohm Semiconductor process. The total harmonic distortion graphs are plotted for three different aspect ratios with different input-voltage amplitudes and different input frequencies. From the simulation results, it is observed that a resistance of approximately 8.52 MΩ can be obtained from supply voltage at  ±0.9 V.

Keywords: Complementary common gate, complementary regulated cascode, current mirror, floating active resistors.

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1335 Metal-Oxide-Semiconductor-Only Process Corner Monitoring Circuit

Authors: Davit Mirzoyan, Ararat Khachatryan

Abstract:

A process corner monitoring circuit (PCMC) is presented in this work. The circuit generates a signal, the logical value of which depends on the process corner only. The signal can be used in both digital and analog circuits for testing and compensation of process variations (PV). The presented circuit uses only metal-oxide-semiconductor (MOS) transistors, which allow increasing its detection accuracy, decrease power consumption and area. Due to its simplicity the presented circuit can be easily modified to monitor parametrical variations of only n-type and p-type MOS (NMOS and PMOS, respectively) transistors, resistors, as well as their combinations. Post-layout simulation results prove correct functionality of the proposed circuit, i.e. ability to monitor the process corner (equivalently die-to-die variations) even in the presence of within-die variations.

Keywords: Detection, monitoring, process corner, process variation.

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1334 Characterization of Responsivity, Sensitivity and Spectral Response in Thin Film SOI photo-BJMOS -FET Compatible with CMOS Technology

Authors: Hai-Qing Xie, Yun Zeng, Yong-Hong Yan, Jian-Ping Zeng, Tai-Hong Wang

Abstract:

Photo-BJMOSFET (Bipolar Junction Metal-Oxide- Semiconductor Field Effect Transistor) fabricated on SOI film was proposed. ITO film is adopted in the device as gate electrode to reduce light absorption. Depletion region but not inversion region is formed in film by applying gate voltage (but low reverse voltage) to achieve high photo-to-dark-current ratio. Comparisons of photoelectriccharacteristics executed among VGK=0V, 0.3V, 0.6V, 0.9V and 1.0V (reverse voltage VAK is equal to 1.0V for total area of 10×10μm2). The results indicate that the greatest improvement in photo-to-dark-current ratio is achieved up to 2.38 at VGK=0.6V. In addition, photo-BJMOSFET is compatible with CMOS integration due to big input resistance

Keywords: Photo-BJMOSFET, Responsivity, Sensitivity, Spectral response.

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1333 Hybrid Prefix Adder Architecture for Minimizing the Power Delay Product

Authors: P.Ramanathan, P.T.Vanathi

Abstract:

Parallel Prefix addition is a technique for improving the speed of binary addition. Due to continuing integrating intensity and the growing needs of portable devices, low-power and highperformance designs are of prime importance. The classical parallel prefix adder structures presented in the literature over the years optimize for logic depth, area, fan-out and interconnect count of logic circuits. In this paper, a new architecture for performing 8-bit, 16-bit and 32-bit Parallel Prefix addition is proposed. The proposed prefix adder structures is compared with several classical adders of same bit width in terms of power, delay and number of computational nodes. The results reveal that the proposed structures have the least power delay product when compared with its peer existing Prefix adder structures. Tanner EDA tool was used for simulating the adder designs in the TSMC 180 nm and TSMC 130 nm technologies.

Keywords: Parallel Prefix Adder (PPA), Dot operator, Semi-Dotoperator, Complementary Metal Oxide Semiconductor (CMOS), Odd-dot operator, Even-dot operator, Odd-semi-dot operator andEven-semi-dot operator.

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1332 Reversible Binary Arithmetic for Integrated Circuit Design

Authors: D. Krishnaveni, M. Geetha Priya

Abstract:

Application of reversible logic in integrated circuits results in the improved optimization of power consumption. This technology can be put into use in a variety of low power applications such as quantum computing, optical computing, nano-technology, and Complementary Metal Oxide Semiconductor (CMOS) Very Large Scale Integrated (VLSI) design etc. Logic gates are the basic building blocks in the design of any logic network and thus integrated circuits. In this paper, reversible Dual Key Gate (DKG) and Dual key Gate Pair (DKGP) gates that work singly as full adder/full subtractor are used to realize the basic building blocks of logic circuits. Reversible full adder/subtractor and parallel adder/ subtractor are designed using other reversible gates available in the literature and compared with that of DKG & DKGP gates. Efficient performance of reversible logic circuits relies on the optimization of the key parameters viz number of constant inputs, garbage outputs and number of reversible gates. The full adder/subtractor and parallel adder/subtractor design with reversible DKGP and DKG gates results in least number of constant inputs, garbage outputs, and number of reversible gates compared to the other designs. Thus, this paper provides a threshold to build more complex arithmetic systems using these reversible logic gates, leading to the enhanced performance of computing systems.

Keywords: Low power CMOS, quantum computing, reversible logic gates, full adder, full subtractor, parallel adder/subtractor, basic gates, universal gates.

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1331 Design of an Ultra Low Power Low Phase Noise CMOS LC Oscillator

Authors: Mahdi Ebrahimzadeh

Abstract:

In this paper we introduce an ultra low power CMOS LC oscillator and analyze a method to design a low power low phase noise complementary CMOS LC oscillator. A 1.8GHz oscillator is designed based on this analysis. The circuit has power supply equal to 1.1 V and dissipates 0.17 mW power. The oscillator is also optimized for low phase noise behavior. The oscillator phase noise is -126.2 dBc/Hz and -144.4 dBc/Hz at 1 MHz and 8 MHz offset respectively.

Keywords: LC oscillator, Low Power, Low Phase Noise

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1330 Interplay of Power Management at Core and Server Level

Authors: Jörg Lenhardt, Wolfram Schiffmann, Jörg Keller

Abstract:

While the feature sizes of recent Complementary Metal Oxid Semiconductor (CMOS) devices decrease the influence of static power prevails their energy consumption. Thus, power savings that benefit from Dynamic Frequency and Voltage Scaling (DVFS) are diminishing and temporal shutdown of cores or other microchip components become more worthwhile. A consequence of powering off unused parts of a chip is that the relative difference between idle and fully loaded power consumption is increased. That means, future chips and whole server systems gain more power saving potential through power-aware load balancing, whereas in former times this power saving approach had only limited effect, and thus, was not widely adopted. While powering off complete servers was used to save energy, it will be superfluous in many cases when cores can be powered down. An important advantage that comes with that is a largely reduced time to respond to increased computational demand. We include the above developments in a server power model and quantify the advantage. Our conclusion is that strategies from datacenters when to power off server systems might be used in the future on core level, while load balancing mechanisms previously used at core level might be used in the future at server level.

Keywords: Power efficiency, static power consumption, dynamic power consumption, CMOS.

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1329 Complementary Energy Path Adiabatic Logic based Full Adder Circuit

Authors: Shipra Upadhyay , R. K. Nagaria, R. A. Mishra

Abstract:

In this paper, we present the design and experimental evaluation of complementary energy path adiabatic logic (CEPAL) based 1 bit full adder circuit. A simulative investigation on the proposed full adder has been done using VIRTUOSO SPECTRE simulator of cadence in 0.18μm UMC technology and its performance has been compared with the conventional CMOS full adder circuit. The CEPAL based full adder circuit exhibits the energy saving of 70% to the conventional CMOS full adder circuit, at 100 MHz frequency and 1.8V operating voltage.

Keywords: Adiabatic, CEPAL, full adder, power clock

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1328 CMOS-Compatible Plasmonic Nanocircuits for On-Chip Integration

Authors: Shiyang Zhu, G. Q. Lo, D. L. Kwong

Abstract:

Silicon photonics is merging as a unified platform for driving photonic based telecommunications and for local photonic based interconnect but it suffers from large footprint as compared with the nanoelectronics. Plasmonics is an attractive alternative for nanophotonics. In this work, two CMOS compatible plasmonic waveguide platforms are compared. One is the horizontal metal-insulator-Si-insulator-metal nanoplasmonic waveguide and the other is metal-insulator-Si hybrid plasmonic waveguide. Various passive and active photonic devices have been experimentally demonstrated based on these two plasmonic waveguide platforms.

Keywords: Plasmonics, on-chip integration, Silicon photonics.

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1327 Formation of Protective Aluminum-Oxide Layer on the Surface of Fe-Cr-Al Sintered-Metal-Fibers via Multi-Stage Thermal Oxidation

Authors: Loai Ben Naji, Osama M. Ibrahim, Khaled J. Al-Fadhalah

Abstract:

The objective of this paper is to investigate the formation and adhesion of a protective aluminum-oxide (Al2O3, alumina) layer on the surface of Iron-Chromium-Aluminum Alloy (Fe-Cr-Al) sintered-metal-fibers. The oxide-scale layer was developed via multi-stage thermal oxidation at 930 oC for 1 hour, followed by 1 hour at 960 oC, and finally at 990 oC for 2 hours. Scanning Electron Microscope (SEM) images show that the multi-stage thermal oxidation resulted in the formation of predominantly Al2O3 platelets-like and whiskers. SEM images also reveal non-uniform oxide-scale growth on the surface of the fibers. Furthermore, peeling/spalling of the alumina protective layer occurred after minimum handling, which indicates weak adhesion forces between the protective layer and the base metal alloy.  Energy Dispersive Spectroscopy (EDS) analysis of the heat-treated Fe-Cr-Al sintered-metal-fibers confirmed the high aluminum content on the surface of the protective layer, and the low aluminum content on the exposed base metal alloy surface. In conclusion, the failure of the oxide-scale protective layer exposes the base metal alloy to further oxidation, and the fragile non-uniform oxide-scale is not suitable as a support for catalysts.

Keywords: High-temperature oxidation, alumina protective layer, iron-chromium-aluminum alloy, sintered-metal-fibers.

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1326 A 1.8 V RF CMOS Active Inductor with 0.18 um CMOS Technology

Authors: Siavash Heydarzadeh, Massoud Dousti

Abstract:

A active inductor in CMOS techonology with a supply voltage of 1.8V is presented. The value of the inductance L can be in the range from 0.12nH to 0.25nH in high frequency(HF). The proposed active inductor is designed in TSMC 0.18-um CMOS technology. The power dissipation of this inductor can retain constant at all operating frequency bands and consume around 20mW from 1.8V power supply. Inductors designed by integrated circuit occupy much smaller area, for this reason,attracted researchers attention for more than decade. In this design we used Advanced Designed System (ADS) for simulating cicuit.

Keywords: CMOS active inductor , 0.18um CMOS technology , ADS

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1325 Preparation of Porous Metal Membrane by Thermal Annealing for Thin Film Encapsulation

Authors: Jaibir Sharma, Lee JaeWung, Merugu Srinivas, Navab Singh

Abstract:

This paper presents thermal annealing de-wetting technique for the preparation of porous metal membrane for Thin Film Encapsulation (TFE) application. Thermal annealing de-wetting experimental results reveal that pore size formation in porous metal membrane depend upon i.e. 1. The substrate at which metal is deposited, 2. Melting point of metal used for porous metal cap layer membrane formation, 3. Thickness of metal used for cap layer, 4. Temperature used for formation of porous metal membrane. In order to demonstrate this technique, Silver (Ag) was used as a metal for preparation of porous metal membrane on amorphous silicon (a-Si) and silicon oxide. The annealing of the silver thin film of various thicknesses was performed at different temperature. Pores in porous silver film were analyzed using Scanning Electron Microscope (SEM). In order to check the usefulness of porous metal film for TFE application, the porous silver film prepared on amorphous silicon (a- Si) and silicon oxide was released using XeF2 and VHF, respectively. Finally, guide line and structures are suggested to use this porous membrane for robust TFE application.

Keywords: De-wetting, thermal annealing, metal, melting point, porous.

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1324 CMOS-Compatible Silicon Nanoplasmonics for On-Chip Integration

Authors: Shiyang Zhu, Guo-Qiang Lo, Dim-Lee Kwong

Abstract:

Although silicon photonic devices provide a significantly larger bandwidth and dissipate a substantially less power than the electronic devices, they suffer from a large size due to the fundamental diffraction limit and the weak optical response of Si. A potential solution is to exploit Si plasmonics, which may not only miniaturize the photonic device far beyond the diffraction limit, but also enhance the optical response in Si due to the electromagnetic field confinement. In this paper, we discuss and summarize the recently developed metal-insulator-Si-insulator-metal nanoplasmonic waveguide as well as various passive and active plasmonic components based on this waveguide, including coupler, bend, power splitter, ring resonator, MZI, modulator, detector, etc. All these plasmonic components are CMOS compatible and could be integrated with electronic and conventional dielectric photonic devices on the same SOI chip. More potential plasmonic devices as well as plasmonic nanocircuits with complex functionalities are also addressed.

Keywords: Silicon nanoplasmonics, Silicon nanophotonics, Onchip integration, CMOS

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1323 Effect of Field Dielectric Material on Performance of InGaAs Power LDMOSFET

Authors: Yashvir Singh, Swati Chamoli

Abstract:

In this paper, a power laterally-diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) on In0.53Ga0.47As is presented. The device utilizes a thicker field-oxide with low dielectric constant under the field-plate in order to achieve possible reduction in device capacitances and reduced-surface-field effect. Using 2D numerical simulations, performance of the proposed device is analyzed and compared with that of the conventional LDMOSFET. The proposed structure provides 50% increase in the breakdown voltage, 21% increase in transit frequency, and 72% improvement in figure-of-merit over the conventional device for same cell pitch.

Keywords: InGaAs, dielectric, lateral, power MOSFET.

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1322 Simulation of High Performance Nanoscale Partially Depleted SOI n-MOSFET Transistors

Authors: Fatima Zohra Rahou, A. Guen Bouazza, B. Bouazza

Abstract:

Invention of transistor is the foundation of electronics industry. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been the key for the development of nanoelectronics technology. In the first part of this manuscript, we present a new generation of MOSFET transistors based on SOI (Silicon-On-Insulator) technology. It is a partially depleted Silicon-On-Insulator (PD SOI MOSFET) transistor simulated by using SILVACO software. This work was completed by the presentation of some results concerning the influence of parameters variation (channel length L and gate oxide thickness Tox) on our PDSOI n-MOSFET structure on its drain current and kink effect.

Keywords: SOI technology, PDSOI MOSFET, FDSOI MOSFET, Kink Effect, SILVACO TCAD.

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1321 Efficiency Enhancement of PWM Controlled Water Electrolysis Cells

Authors: S.K. Mazloomi, Nasri b. Sulaiman

Abstract:

By analyzing the sources of energy and power loss in PWM (Pulse Width Modulation) controlled drivers of water electrolysis cells, it is possible to reduce the power dissipation and enhance the efficiency of such hydrogen production units. A PWM controlled power driver is based on a semiconductor switching element where its power dissipation might be a remarkable fraction of the total power demand of an electrolysis system. Power dissipation in a semiconductor switching element is related to many different parameters which could be fitted into two main categories: switching losses and conduction losses. Conduction losses are directly related to the built, structure and capabilities of a switching device itself and indeed the conditions in which the element is handling the switching application such as voltage, current, temperature and of course the fabrication technology. On the other hand, switching losses have some other influencing variables other than the mentioned such as control system, switching method and power electronics circuitry of the PWM power driver. By analyzings the characteristics of recently developed power switching transistors from different families of Bipolar Junction Transistors (BJT), Metal Oxide Semiconductor Field Effect Transistors (MOSFET) and Insulated Gate Bipolar Transistors (IGBT), some recommendations are made in this paper which are able to lead to achieve higher hydrogen production efficiency by utilizing PWM controlled water electrolysis cells.

Keywords: Power switch, PWM, Semiconductor switch, Waterelectrolysis

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1320 Design of a CMOS Differential Operational Transresistance Amplifier in 90 nm CMOS Technology

Authors: Hafiz Muhammad Obaid, Umais Tayyab, Shabbir Majeed Ch.

Abstract:

In this paper, a CMOS differential operational transresistance amplifier (OTRA) is presented. The amplifier is designed and implemented in a standard umc90-nm CMOS technology. The differential OTRA provides wider bandwidth at high gain. It also shows much better rise and fall time and exhibits a very good input current dynamic range of 50 to 50 μA. The OTRA can be used in many analog VLSI applications. The presented amplifier has high gain bandwidth product of 617.6 THz Ω. The total power dissipation of the presented amplifier is also very low and it is 0.21 mW.

Keywords: CMOS, differential, operational transresistance amplifier, OTRA, 90 nm, VLSI.

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1319 A Single-Phase Register File with Complementary Pass-Transistor Adiabatic Logic

Authors: Jianping Hu, Xiaolei Sheng

Abstract:

This paper introduces an adiabatic register file based on two-phase CPAL (Complementary Pass-Transistor Adiabatic Logic circuits) with power-gating scheme, which can operate on a single-phase power clock. A 32×32 single-phase adiabatic register file with power-gating scheme has been implemented with TSMC 0.18μm CMOS technology. All the circuits except for the storage cells employ two-phase CPAL circuits, and the storage cell is based on the conventional memory one. The two-phase non-overlap power-clock generator with power-gating scheme is used to supply the proposed adiabatic register file. Full-custom layouts are drawn. The energy and functional simulations have been performed using the net-list extracted from their layouts. Compared with the traditional static CMOS register file, HSPICE simulations show that the proposed adiabatic register file can work very well, and it attains about 73% energy savings at 100 MHz.

Keywords: Low power, Register file, Complementarypass-transistor logic, Adiabatic logic, Single-phase power clock.

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1318 Depletion Layer Parameters of Al-MoO3-P-CdTe-Al MOS Structures

Authors: A. C. Sarmah

Abstract:

The Al-MoO3-P-CdTe-Al MOS sandwich structures were fabricated by vacuum deposition method on cleaned glass substrates. Capacitance versus voltage measurements were performed at different frequencies and sweep rates of applied voltages for oxide and semiconductor films of different thicknesses. In the negative voltage region of the C-V curve a high differential capacitance of the semiconductor was observed and at high frequencies (<10 kHz) the transition from accumulation to depletion and further to deep depletion was observed as the voltage was swept from negative to positive. A study have been undertaken to determine the value of acceptor density and some depletion layer parameters such as depletion layer capacitance, depletion width, impurity concentration, flat band voltage, Debye length, flat band capacitance, diffusion or built-in-potential, space charge per unit area etc. These were determined from C-V measurements for different oxide and semiconductor thicknesses.

Keywords: Debye length, Depletion width, flat band capacitance, impurity concentration.

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1317 Algorithm Design and Performance Evaluation of Equivalent CMOS Model

Authors: Parvinder S. Sandhu, Iqbaldeep Kaur, Amit Verma, Inderpreet Kaur, Birinderjit S. Kalyan

Abstract:

This work is a proposed model of CMOS for which the algorithm has been created and then the performance evaluation of this proposition has been done. In this context, another commonly used model called ZSTT (Zero Switching Time Transient) model is chosen to compare all the vital features and the results for the Proposed Equivalent CMOS are promising. In the end, the excerpts of the created algorithm are also included

Keywords: Dual Capacitor Model, ZSTT, CMOS, SPICEMacro-Model.

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1316 Propane Dehydrogenation with Better Stability by a Modified Pt-Based Catalyst

Authors: N. Hataivichian, K. Suriye, S. Kunjara Na Ayudhya, P. Praserthdam, S. Phatanasri

Abstract:

The effect of transition metal doping on Pt/Al2O3 catalyst used in propane dehydrogenation reaction at 500°C was studied. The preparation methods investigated were sequential impregnation (Pt followed by the 2nd metal or the 2nd metal followed by Pt) and co-impregnation. The metal contents of these catalysts were fixed as the weight ratio of Pt per the 2nd metal of around 0.075. These catalysts were characterized by N2-physisorption, TPR, COchemisorption and NH3-TPD. It was found that the impregnated 2nd metal had an effect upon reducibility of Pt due to its interaction with transition metal-containing structure. This was in agreement with the CO-chemisorption result that the presence of Pt metal, which is a result from Pt species reduction, was decreased. The total acidity of bimetallic catalysts is decreased but the strong acidity is slightly increased. It was found that the stability of bimetallic catalysts prepared by co-impregnation and sequential impregnation where the 2nd metal was impregnated before Pt were better than that of monometallic catalyst (undoped Pt one) due to the forming of Pt sites located on the transition metal-oxide modified surface. Among all preparation methods, the sequential impregnation method- having Pt impregnated before the 2nd metal gave the worst stability because this catalyst lacked the modified Pt sites and some fraction of Pt sites was covered by the 2nd metal.

Keywords: Alumina, dehydrogenation, platinum, transition metal.

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1315 LFSR Counter Implementation in CMOS VLSI

Authors: Doshi N. A., Dhobale S. B., Kakade S. R.

Abstract:

As chip manufacturing technology is suddenly on the threshold of major evaluation, which shrinks chip in size and performance, LFSR (Linear Feedback Shift Register) is implemented in layout level which develops the low power consumption chip, using recent CMOS, sub-micrometer layout tools. Thus LFSR counter can be a new trend setter in cryptography and is also beneficial as compared to GRAY & BINARY counter and variety of other applications. This paper compares 3 architectures in terms of the hardware implementation, CMOS layout and power consumption, using Microwind CMOS layout tool. Thus it provides solution to a low power architecture implementation of LFSR in CMOS VLSI.

Keywords: Chip technology, Layout level, LFSR, Pass transistor

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1314 Removal of Elemental Mercury from Dry Methane Gas with Manganese Oxides

Authors: Junya Takenami, Md. Azhar Uddin, Eiji Sasaoka, Yasushi Shioya, Tsuneyoshi Takase

Abstract:

In this study, we sought to investigate the mercury removal efficiency of manganese oxides from natural gas. The fundamental studies on mercury removal with manganese oxides sorbents were carried out in a laboratory scale fixed bed reactor at 30 °C with a mixture of methane (20%) and nitrogen gas laden with 4.8 ppb of elemental mercury. Manganese oxides with varying surface area and crystalline phase were prepared by conventional precipitation method in this study. The effects of surface area, crystallinity and other metal oxides on mercury removal efficiency were investigated. Effect of Ag impregnation on mercury removal efficiency was also investigated. Ag supported on metal oxide such titania and zirconia as reference materials were also used in this study for comparison. The characteristics of mercury removal reaction with manganese oxide was investigated using a temperature programmed desorption (TPD) technique. Manganese oxides showed very high Hg removal activity (about 73-93% Hg removal) for first time use. Surface area of the manganese oxide samples decreased after heat-treatment and resulted in complete loss of Hg removal ability for repeated use after Hg desorption in the case of amorphous MnO2, and 75% loss of the initial Hg removal activity for the crystalline MnO2. Mercury desorption efficiency of crystalline MnO2 was very low (37%) for first time use and high (98%) after second time use. Residual potassium content in MnO2 may have some effect on the thermal stability of the adsorbed Hg species. Desorption of Hg from manganese oxides occurs at much higher temperatures (with a peak at 400 °C) than Ag/TiO2 or Ag/ZrO2. Mercury may be captured on manganese oxides in the form of mercury manganese oxide.

Keywords: Mercury removal, Metal and metal oxide sorbents, Methane, Natural gas.

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1313 Optimization of HALO Structure Effects in 45nm p-type MOSFETs Device Using Taguchi Method

Authors: F. Salehuddin, I. Ahmad, F. A. Hamid, A. Zaharim, H. A. Elgomati, B. Y. Majlis, P. R. Apte

Abstract:

In this study, the Taguchi method was used to optimize the effect of HALO structure or halo implant variations on threshold voltage (VTH) and leakage current (ILeak) in 45nm p-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) device. Besides halo implant dose, the other process parameters which used were Source/Drain (S/D) implant dose, oxide growth temperature and silicide anneal temperature. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with Taguchi method to aid in design and optimize the process parameters. In this research, the most effective process parameters with respect to VTH and ILeak are halo implant dose (40%) and S/D implant dose (52%) respectively. Whereas the second ranking factor affecting VTH and ILeak are oxide growth temperature (32%) and halo implant dose (34%) respectively. The results show that after optimizations approaches is -0.157V at ILeak=0.195mA/μm.

Keywords: Optimization, p-type MOSFETs device, HALO Structure, Taguchi Method.

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1312 The Design of PFM Mode DC-DC Converter with DT-CMOS Switch

Authors: Jae-Chang Kwak, Yong-Seo Koo

Abstract:

The high efficiency power management IC (PMIC) with switching device is presented in this paper. PMIC is controlled with PFM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS (DT-CMOS) with low on-resistance is designed to decrease conduction loss. The threshold voltage of DT-CMOS drops as the gate voltage increase, resulting in a much higher current handling capability than standard MOSFET. PFM control circuits consist of a generator, AND gate and comparator. The generator is made to have 1.2MHz oscillation voltage. The DC-DC converter based on PFM control circuit and low on-resistance switching device is presented in this paper.

Keywords: DT-CMOS, PMIC, PFM, DC-DC converter.

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