@article{(Open Science Index):https://publications.waset.org/pdf/5272, title = {Hybrid Prefix Adder Architecture for Minimizing the Power Delay Product}, author = {P.Ramanathan and P.T.Vanathi}, country = {}, institution = {}, abstract = {Parallel Prefix addition is a technique for improving the speed of binary addition. Due to continuing integrating intensity and the growing needs of portable devices, low-power and highperformance designs are of prime importance. The classical parallel prefix adder structures presented in the literature over the years optimize for logic depth, area, fan-out and interconnect count of logic circuits. In this paper, a new architecture for performing 8-bit, 16-bit and 32-bit Parallel Prefix addition is proposed. The proposed prefix adder structures is compared with several classical adders of same bit width in terms of power, delay and number of computational nodes. The results reveal that the proposed structures have the least power delay product when compared with its peer existing Prefix adder structures. Tanner EDA tool was used for simulating the adder designs in the TSMC 180 nm and TSMC 130 nm technologies.}, journal = {International Journal of Electronics and Communication Engineering}, volume = {3}, number = {4}, year = {2009}, pages = {869 - 873}, ee = {https://publications.waset.org/pdf/5272}, url = {https://publications.waset.org/vol/28}, bibsource = {https://publications.waset.org/}, issn = {eISSN: 1307-6892}, publisher = {World Academy of Science, Engineering and Technology}, index = {Open Science Index 28, 2009}, }