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Complementary Energy Path Adiabatic Logic based Full Adder Circuit

Authors: Shipra Upadhyay, R. K. Nagaria, R. A. Mishra

Abstract:

In this paper, we present the design and experimental evaluation of complementary energy path adiabatic logic (CEPAL) based 1 bit full adder circuit. A simulative investigation on the proposed full adder has been done using VIRTUOSO SPECTRE simulator of cadence in 0.18μm UMC technology and its performance has been compared with the conventional CMOS full adder circuit. The CEPAL based full adder circuit exhibits the energy saving of 70% to the conventional CMOS full adder circuit, at 100 MHz frequency and 1.8V operating voltage.

Keywords: full adder, Adiabatic, CEPAL, power clock

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1334033

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