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Hybrid Prefix Adder Architecture for Minimizing the Power Delay Product

Authors: P.Ramanathan, P.T.Vanathi

Abstract:

Parallel Prefix addition is a technique for improving the speed of binary addition. Due to continuing integrating intensity and the growing needs of portable devices, low-power and highperformance designs are of prime importance. The classical parallel prefix adder structures presented in the literature over the years optimize for logic depth, area, fan-out and interconnect count of logic circuits. In this paper, a new architecture for performing 8-bit, 16-bit and 32-bit Parallel Prefix addition is proposed. The proposed prefix adder structures is compared with several classical adders of same bit width in terms of power, delay and number of computational nodes. The results reveal that the proposed structures have the least power delay product when compared with its peer existing Prefix adder structures. Tanner EDA tool was used for simulating the adder designs in the TSMC 180 nm and TSMC 130 nm technologies.

Keywords: Parallel Prefix Adder (PPA), Dot operator, Semi-Dotoperator, Complementary Metal Oxide Semiconductor (CMOS), Odd-dot operator, Even-dot operator, Odd-semi-dot operator andEven-semi-dot operator.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1060741

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References:


[1] Haikun Zhu, Chung-Kuan Cheng and Ronald Graham, "Constructing Zero Deficiency Parallel Prefix adder of Minimum Depth," Proceedings of 2005 Asia South Pacific Design Automation Conference, 2005, pp. 883-888.
[2] Matthew Ziegler, Mircea Stan, "Optimal Logarithmic Adder structures with a fan-out of two for minimizing area delay product," IEEE 2001.
[3] J. Sklansky, "Conditional Sum Addition Logic," IRE Transactions on Electronic computers, vol. EC-9, 1960, pp. 226-231.
[4] P.Kogge and H.Stone, "A Parallel Algorithm for the efficient solution of a general class of recurrence relations," IEEE Transactions on Computers, vol. C-22, no.8, August 1973, pp.786-793.
[5] R.Brent and H.Kung, "A Regular Layout for Parallel adders," IEEE Transaction on Computers, vol. C-31, no.3, March 1982, pp. 260-264.
[6] T. Han and D. Carlson, "Fast Area Efficient VLSI adders," Proceedings of the 8th Symposium on Computer Arithmetic, September 1987, pp.49- 56.
[7] S.Knowles, "A Family of Adders", Proceeding of the 15th IEEE Symposium on Computer Arithmetic, June 2001, pp.277-281.
[8] R. Ladner and M. Fischer, "Parallel Prefix Computation," Journal of ACM, vol.27,no.4, October 1980, pp. 831-838.
[9] Giorgos Dimitrakopoulos and Dimitris Nikolos, "High Speed Parallel Prefix VLSI Ling adders," IEEE Transactions on Computers, vol.54, no.2, February 2005, pp. 225-231.
[10] David Harris, " A Taxonomy of Parallel Prefix Networks," Proceedings of the 37th Asilomar Conference on Signals, Systems and Computers, 2003, pp.2213-2217.