{"title":"Hybrid Prefix Adder Architecture for Minimizing the Power Delay Product","authors":"P.Ramanathan, P.T.Vanathi","volume":28,"journal":"International Journal of Electronics and Communication Engineering","pagesStart":869,"pagesEnd":874,"ISSN":"1307-6892","URL":"https:\/\/publications.waset.org\/pdf\/5272","abstract":"Parallel Prefix addition is a technique for improving\r\nthe speed of binary addition. Due to continuing integrating intensity\r\nand the growing needs of portable devices, low-power and highperformance\r\ndesigns are of prime importance. The classical parallel\r\nprefix adder structures presented in the literature over the years\r\noptimize for logic depth, area, fan-out and interconnect count of logic\r\ncircuits. In this paper, a new architecture for performing 8-bit, 16-bit\r\nand 32-bit Parallel Prefix addition is proposed. The proposed prefix\r\nadder structures is compared with several classical adders of same\r\nbit width in terms of power, delay and number of computational\r\nnodes. The results reveal that the proposed structures have the least\r\npower delay product when compared with its peer existing Prefix\r\nadder structures. Tanner EDA tool was used for simulating the adder\r\ndesigns in the TSMC 180 nm and TSMC 130 nm technologies.","references":"[1] Haikun Zhu, Chung-Kuan Cheng and Ronald Graham, \"Constructing\r\nZero Deficiency Parallel Prefix adder of Minimum Depth,\" Proceedings\r\nof 2005 Asia South Pacific Design Automation Conference, 2005, pp.\r\n883-888.\r\n[2] Matthew Ziegler, Mircea Stan, \"Optimal Logarithmic Adder structures\r\nwith a fan-out of two for minimizing area delay product,\" IEEE 2001.\r\n[3] J. Sklansky, \"Conditional Sum Addition Logic,\" IRE Transactions on\r\nElectronic computers, vol. EC-9, 1960, pp. 226-231.\r\n[4] P.Kogge and H.Stone, \"A Parallel Algorithm for the efficient solution of\r\na general class of recurrence relations,\" IEEE Transactions on\r\nComputers, vol. C-22, no.8, August 1973, pp.786-793.\r\n[5] R.Brent and H.Kung, \"A Regular Layout for Parallel adders,\" IEEE\r\nTransaction on Computers, vol. C-31, no.3, March 1982, pp. 260-264.\r\n[6] T. Han and D. Carlson, \"Fast Area Efficient VLSI adders,\" Proceedings\r\nof the 8th Symposium on Computer Arithmetic, September 1987, pp.49-\r\n56.\r\n[7] S.Knowles, \"A Family of Adders\", Proceeding of the 15th IEEE\r\nSymposium on Computer Arithmetic, June 2001, pp.277-281.\r\n[8] R. Ladner and M. Fischer, \"Parallel Prefix Computation,\" Journal of\r\nACM, vol.27,no.4, October 1980, pp. 831-838.\r\n[9] Giorgos Dimitrakopoulos and Dimitris Nikolos, \"High Speed Parallel\r\nPrefix VLSI Ling adders,\" IEEE Transactions on Computers, vol.54,\r\nno.2, February 2005, pp. 225-231.\r\n[10] David Harris, \" A Taxonomy of Parallel Prefix Networks,\" Proceedings\r\nof the 37th Asilomar Conference on Signals, Systems and Computers,\r\n2003, pp.2213-2217.","publisher":"World Academy of Science, Engineering and Technology","index":"Open Science Index 28, 2009"}