%0 Journal Article %A Yngvar Berg and Omid Mirmotahari %D 2012 %J International Journal of Electronics and Communication Engineering %B World Academy of Science, Engineering and Technology %I Open Science Index 68, 2012 %T High Speed and Ultra Low-voltage CMOS NAND and NOR Domino Gates %U https://publications.waset.org/pdf/852 %V 68 %X In this paper we ultra low-voltage and high speed CMOS domino logic. For supply voltages below 500mV the delay for a ultra low-voltage NAND2 gate is aproximately 10% of a complementary CMOS inverter. Furthermore, the delay variations due to mismatch is much less than for conventional CMOS. Differential domino gates for AND/NAND and OR/NOR operation are presented. %P 760 - 763