Metal-Oxide-Semiconductor-Only Process Corner Monitoring Circuit

Authors: Davit Mirzoyan, Ararat Khachatryan

Abstract:

A process corner monitoring circuit (PCMC) is presented in this work. The circuit generates a signal, the logical value of which depends on the process corner only. The signal can be used in both digital and analog circuits for testing and compensation of process variations (PV). The presented circuit uses only metal-oxide-semiconductor (MOS) transistors, which allow increasing its detection accuracy, decrease power consumption and area. Due to its simplicity the presented circuit can be easily modified to monitor parametrical variations of only n-type and p-type MOS (NMOS and PMOS, respectively) transistors, resistors, as well as their combinations. Post-layout simulation results prove correct functionality of the proposed circuit, i.e. ability to monitor the process corner (equivalently die-to-die variations) even in the presence of within-die variations.

Keywords: Detection, monitoring, process corner, process variation.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1128917

References:

[1] T. Chen, “Challenges for silicon technology scaling in the Nanoscale Era,” Proc. of ESSCIRC, pp. 1-7, Sept. 2009.
[2] Y. Li, Ch. Hwang, T. Li, M. Han, “Process-Variation Effect, Metal-Gate Work-Function Fluctuation, and Random-Dopant Fluctuation in Emerging CMOS Technologies,” IEEE Trans. on Electron Devices, pp. 437 – 447, Feb. 2010.
[3] Y. Ohnari, A.A. Khan, A. Dutta, M. M. Mattausch, H. J. Mattausch, “Die-to-die and within-die variation extraction for circuit simulation with surface-potential compact model,” IEEE Int. Conf. on Microelectronic Test Structures (ICMTS), pp. 146-150, March 2013.
[4] L. Pang, B. Nikolic, “Measurements and analysis of process variability in 90nm CMOS,” IEEE J. Solid-State Circuits, pp.1655-1663, May 2009.
[5] C. H. Kim, K. Roy, S. Hsu, R. Krishnamurthy, S. Borkar, “A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits,” IEEE Trans. on VLSI Systems, pp.646-649, 2006.
[6] K. Kim, F. Ge, K. Choi, “On-chip process variation monitoring circuit based on gate leakage sensing”, Electronics Letters, pp. 235 – 236, 2010.
[7] A. Ghosh, R. M. Rao, J. J. Kim, Ch. Chuang, R. B. Brown, “Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection,” IEEE Trans. on VLSI Systems, pp. 1683-1692, 2013.
[8] Ch. Chen, H. Tseng, R. Kuo, Ch. Wang, “On-chip MOS PVT variation monitor for slew rate self-adjusting 2×VDD output buffers,” IEEE Int. Conf. on IC Design & Technology, pp.1-4, 2012.
[9] H. Mostafa, M. Anis, M. Elmasry, “On-Chip Process Variations Compensation Using an Analog Adaptive Body Bias (A-ABB),” IEEE Trans. on VLSI Systems, pp. 770 – 774, April 2012.
[10] B. Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw- Hill Education, 2016.
[11] N.Z. Butt, J.B. Johnson, “Modeling and Analysis of Transistor Mismatch Due to Variability in Short-Channel Effect Induced by Random Dopant Fluctuation,” IEEE Electron Device Letters, pp.1099-1101, Aug. 2012.
[12] H. Li, H. Chen, Q. Dong, L. Chen, J. Wang, J. Kim, Sh. Yu, J. Wu, Y. LinBashir, L. Milor, “Process optimization for random threshold voltage variation reduction in nanoscale MOSFET by 3D simulation,” IEEE 11th Int. Conf. on Solid-State and Integrated Circuit Technology (ICSICT), pp.1-3, Oct. 2012.