Commenced in January 2007
Paper Count: 30172
LFSR Counter Implementation in CMOS VLSI
Abstract:As chip manufacturing technology is suddenly on the threshold of major evaluation, which shrinks chip in size and performance, LFSR (Linear Feedback Shift Register) is implemented in layout level which develops the low power consumption chip, using recent CMOS, sub-micrometer layout tools. Thus LFSR counter can be a new trend setter in cryptography and is also beneficial as compared to GRAY & BINARY counter and variety of other applications. This paper compares 3 architectures in terms of the hardware implementation, CMOS layout and power consumption, using Microwind CMOS layout tool. Thus it provides solution to a low power architecture implementation of LFSR in CMOS VLSI.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1332312Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 4038
 A circuits & systems perspective "CMOS VLSI design" by Neil Weste, Harris & Banerjee.
 "Basic CMOS Cell Design" by Etienne Sicard & Sonia Delmas Bendhia.
 "CMOS Digital Integrated Circuits-Analysis and design" by Sung-MO Kang & Yusuf Leblebici.
 "Digital Design-Principles and Practices" by John F. Wakerly.
 "Principles &Applications of CMOS Logic" by Neil Weste & Karmran.
 James L. Massey, "On the Shift register Synthesis & BCH Decoding", IEEE Trans. Inform. Theory, vol. IT-15, n. 1, pp. 122-127, Jan 1969.
 "LFSR Layout" Advance VLSI Design, Dept of Elect Engg.University of Houston
 A Project report of"4017 CMOS LED CHASERCOUNTER" Layout in Cadence by Arshdeep Singh, Oscar Servin, Edward Lee, Lutfi Bustami.
 A White Paper on "Linear Feedback Shift Registers and Cyclic Codes" in SAGE Timothy Brian Brock.
 A white Paper on "Deterministic Built-in Test Pattern Generation for High-Performance Circuits Using Twisted- Ring Counters" by Krishnendu Chakrabarty,Brian T. Murray, and Vikram Iyengar.
 Kazuo Yano," Top down pass-Transistor Logic Design," IEEE Journal of solid-state circuits, vol-31,No-6, june 1996.
 Kazuo Yano," A 3.8 CMOS 16 * 16 -b multiplier using complementary pass-transistor Logic" IEEE Journal of solid-state circuits, vol-25,No-2, April 1990.
 "Micro wind User Manual"
 Advanced CMOS Cell Design" by Etienne Sicard, & Sonia Delmas Bendhia.