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Design and Characterization of a CMOS Process Sensor Utilizing Vth Extractor Circuit

Authors: Rohana Musa, Yuzman Yusoff, Chia Chieu Yin, Hanif Che Lah

Abstract:

This paper presents the design and characterization of a low power Complementary Metal Oxide Semiconductor (CMOS) process sensor. The design is targeted for implementation using Silterra’s 180 nm CMOS process technology. The proposed process sensor employs a voltage threshold (Vth) extractor architecture for detection of variations in the fabrication process. The process sensor generates output voltages in the range of 401 mV (fast-fast corner) to 443 mV (slow-slow corner) at nominal condition. The power dissipation for this process sensor is 6.3 µW with a supply voltage of 1.8V with a silicon area of 190 µm X 60 µm. The preliminary result of this process sensor that was fabricated indicates a close resemblance between test and simulated results.

Keywords: CMOS Process sensor, Process, Voltage and Temperature (PVT) sensor, threshold extractor circuit, Vth extractor circuit.

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References:


[1] C Shi-Wen, MH Chang, W Hsieh, W Hwang, et al., “Fully on-chip temperature, process, and voltage sensors," IEEE International Symposium on Circuits and Systems, June 2010.
[2] Qadeer A. Khan, G. K. Siddhartha, Divya Tripathi, Sanjay Kumar Wadhwa and Kulbhushan Misri, “Techniques for on-chip process voltage and temperature detection and compensation”, Proc. IEEE VLSID, pp. 581-586, 2006.
[3] Sang-Soo Lee, Edward Boling, Augustine Kuo and Robert Rogenmoser, “A slew-rate based process monitor and bi-directional body bias circuit for adaptive body biasing in SoC applications”, Proc. IEEE CICC, pp. 1-4, 2013.
[4] Chih-Lin Chen, Hsin-Yuan Tseng, Ron-Chi Kuo and Chua-Chin Wang, “On-chip MOS PVT variation monitor for slew rate self-adjusting 2xVDD output buffers”, Proc. IEEE ICICDT, pp. 1-4, 2012.
[5] Chua-Chin Wang, Wen-Je Lu and Hsin-Yuan Tseng, “A high-speed 2xVDD output buffer with PVT detection using 40-nm CMOS technology”, Proc. IEEE ISCAS, pp. 2079-2082, 2013.
[6] Z. Wang, “Automatic I i. extractors based on an n x n2 MOS transistor array and their application,” IEEE J. Solid-Srafe Circuits, vol. 27, no. 9, pp. 1277-1285, Sept. 1992.
[7] Mark G. Johnson, et al., "An input-free VT extractor circuit using a two-transistor differential amplifier," IEEE journal of solid-state circuits, vol.28, No.6, June 1993.