Search results for: full subtractor
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 652

Search results for: full subtractor

652 Reversible Binary Arithmetic for Integrated Circuit Design

Authors: D. Krishnaveni, M. Geetha Priya

Abstract:

Application of reversible logic in integrated circuits results in the improved optimization of power consumption. This technology can be put into use in a variety of low power applications such as quantum computing, optical computing, nano-technology, and Complementary Metal Oxide Semiconductor (CMOS) Very Large Scale Integrated (VLSI) design etc. Logic gates are the basic building blocks in the design of any logic network and thus integrated circuits. In this paper, reversible Dual Key Gate (DKG) and Dual key Gate Pair (DKGP) gates that work singly as full adder/full subtractor are used to realize the basic building blocks of logic circuits. Reversible full adder/subtractor and parallel adder/ subtractor are designed using other reversible gates available in the literature and compared with that of DKG & DKGP gates. Efficient performance of reversible logic circuits relies on the optimization of the key parameters viz number of constant inputs, garbage outputs and number of reversible gates. The full adder/subtractor and parallel adder/subtractor design with reversible DKGP and DKG gates results in least number of constant inputs, garbage outputs, and number of reversible gates compared to the other designs. Thus, this paper provides a threshold to build more complex arithmetic systems using these reversible logic gates, leading to the enhanced performance of computing systems.

Keywords: Low power CMOS, quantum computing, reversible logic gates, full adder, full subtractor, parallel adder/subtractor, basic gates, universal gates.

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651 Complementary Energy Path Adiabatic Logic based Full Adder Circuit

Authors: Shipra Upadhyay , R. K. Nagaria, R. A. Mishra

Abstract:

In this paper, we present the design and experimental evaluation of complementary energy path adiabatic logic (CEPAL) based 1 bit full adder circuit. A simulative investigation on the proposed full adder has been done using VIRTUOSO SPECTRE simulator of cadence in 0.18μm UMC technology and its performance has been compared with the conventional CMOS full adder circuit. The CEPAL based full adder circuit exhibits the energy saving of 70% to the conventional CMOS full adder circuit, at 100 MHz frequency and 1.8V operating voltage.

Keywords: Adiabatic, CEPAL, full adder, power clock

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650 Two New Low Power High Performance Full Adders with Minimum Gates

Authors: M.Hosseinghadiry, H. Mohammadi, M.Nadisenejani

Abstract:

with increasing circuits- complexity and demand to use portable devices, power consumption is one of the most important parameters these days. Full adders are the basic block of many circuits. Therefore reducing power consumption in full adders is very important in low power circuits. One of the most powerconsuming modules in full adders is XOR/XNOR circuit. This paper presents two new full adders based on two new logic approaches. The proposed logic approaches use one XOR or XNOR gate to implement a full adder cell. Therefore, delay and power will be decreased. Using two new approaches and two XOR and XNOR gates, two new full adders have been implemented in this paper. Simulations are carried out by HSPICE in 0.18μm bulk technology with 1.8V supply voltage. The results show that the ten-transistors proposed full adder has 12% less power consumption and is 5% faster in comparison to MB12T full adder. 9T is more efficient in area and is 24% better than similar 10T full adder in term of power consumption. The main drawback of the proposed circuits is output threshold loss problem.

Keywords: Full adder, XNOR, Low power, High performance, Very Large Scale Integrated Circuit.

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649 A New Efficient Scalable BIST Full Adder using Polymorphic Gates

Authors: M. Mashayekhi, H. H. Ardakani, A. Omidian

Abstract:

Among various testing methodologies, Built-in Self- Test (BIST) is recognized as a low cost, effective paradigm. Also, full adders are one of the basic building blocks of most arithmetic circuits in all processing units. In this paper, an optimized testable 2- bit full adder as a test building block is proposed. Then, a BIST procedure is introduced to scale up the building block and to generate a self testable n-bit full adders. The target design can achieve 100% fault coverage using insignificant amount of hardware redundancy. Moreover, Overall test time is reduced by utilizing polymorphic gates and also by testing full adder building blocks in parallel.

Keywords: BIST, Full Adder, Polymorphic Gate

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648 Demystifying Full-Stack Observability: Mastering Visibility, Insight, and Action in the Modern Digital Landscape

Authors: Ashly Joseph

Abstract:

In the era of digital transformation, full-stack observability has emerged as a crucial aspect of administering modern application stacks. This research paper presents the concept of full-stack observability, its significance in the context of contemporary application stacks, and the challenges posed by swiftly evolving digital environments. In addition, it describes how full-stack observability intends to provide complete visibility and actionable insights by correlating telemetry across multiple domains.

Keywords: Actionable insights, digital transformation, full-stack observability, performance metrics.

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647 High Speed NP-CMOS and Multi-Output Dynamic Full Adder Cells

Authors: Reza Faghih Mirzaee, Mohammad Hossein Moaiyeri, Keivan Navi

Abstract:

In this paper we present two novel 1-bit full adder cells in dynamic logic style. NP-CMOS (Zipper) and Multi-Output structures are used to design the adder blocks. Characteristic of dynamic logic leads to higher speeds than the other standard static full adder cells. Using HSpice and 0.18┬Ám CMOS technology exhibits a significant decrease in the cell delay which can result in a considerable reduction in the power-delay product (PDP). The PDP of Multi-Output design at 1.8v power supply is around 0.15 femto joule that is 5% lower than conventional dynamic full adder cell and at least 21% lower than other static full adders.

Keywords: Bridge Style, Dynamic Logic, Full Adder, HighSpeed, Multi Output, NP-CMOS, Zipper.

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646 Designing of Full Adder Using Low Power Techniques

Authors: Shashank Gautam

Abstract:

This paper proposes techniques like MT CMOS, POWER GATING, DUAL STACK, GALEOR and LECTOR to reduce the leakage power. A Full Adder has been designed using these techniques and power dissipation is calculated and is compared with general CMOS logic of Full Adder. Simulation results show the validity of the proposed techniques is effective to save power dissipation and to increase the speed of operation of the circuits to a large extent.

Keywords: Low Power, MT CMOS, Galeor, Lector, Power Gating, Dual Stack, Full Adder.

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645 Design and Implementation of 4 Bit Multiplier Using Fault Tolerant Hybrid Full Adder

Authors: C. Kalamani, V. Abishek Karthick, S. Anitha, K. Kavin Kumar

Abstract:

The fault tolerant system plays a crucial role in the critical applications which are being used in the present scenario. A fault may change the functionality of circuits. Aim of this paper is to design multiplier using fault tolerant hybrid full adder. Fault tolerant hybrid full adder is designed to check and repair any fault in the circuit using self-checking circuit and the self-repairing circuit. Further, the use of conventional logic circuits may result in more area, delay as well as power consumption. In order to reduce these parameters of the circuit, GDI (Gate Diffusion Input) techniques with less number of transistors are used compared to conventional full adder circuit. This reduces the area, delay and power consumption. The proposed method solves the major problems occurring in the most crucial and critical applications.

Keywords: Gate diffusion input, hybrid full adder, self-checking, fault tolerant.

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644 An Efficient Digital Baseband ASIC for Wireless Biomedical Signals Monitoring

Authors: Kah-Hyong Chang, Xin Liu, Jia Hao Cheong, Saisundar Sankaranarayanan, Dexing Pang, Hongzhao Zheng

Abstract:

A digital baseband Application-Specific Integrated Circuit (ASIC) (yclic Redundancy Checkis developed for a microchip transponder to transmit signals and temperature levels from biomedical monitoring devices. The transmission protocol is adapted from the ISO/IEC 11784/85 standard. The module has a decimation filter that employs only a single adder-subtractor in its datapath. The filtered output is coded with cyclic redundancy check and transmitted through backscattering Load Shift Keying (LSK) modulation to a reader. Fabricated using the 0.18-μm CMOS technology, the module occupies 0.116 mm2 in chip area (digital baseband: 0.060 mm2, decimation filter: 0.056 mm2), and consumes a total of less than 0.9 μW of power (digital baseband: 0.75 μW, decimation filter: 0.14 μW).

Keywords: Biomedical sensor, decimation filter, Radio Frequency Integrated Circuit (RFIC) baseband, temperature sensor.

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643 Prediction of the Torsional Vibration Characteristics of a Rotor-Shaft System Using Its Scale Model and Scaling Laws

Authors: Jia-Jang Wu

Abstract:

This paper presents the scaling laws that provide the criteria of geometry and dynamic similitude between the full-size rotor-shaft system and its scale model, and can be used to predict the torsional vibration characteristics of the full-size rotor-shaft system by manipulating the corresponding data of its scale model. The scaling factors, which play fundamental roles in predicting the geometry and dynamic relationships between the full-size rotor-shaft system and its scale model, for torsional free vibration problems between scale and full-size rotor-shaft systems are firstly obtained from the equation of motion of torsional free vibration. Then, the scaling factor of external force (i.e., torque) required for the torsional forced vibration problems is determined based on the Newton’s second law. Numerical results show that the torsional free and forced vibration characteristics of a full-size rotor-shaft system can be accurately predicted from those of its scale models by using the foregoing scaling factors. For this reason, it is believed that the presented approach will be significant for investigating the relevant phenomenon in the scale model tests.

Keywords: Torsional vibration, full-size model, scale model, scaling laws.

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642 A Novel Low Power, High Speed 14 Transistor CMOS Full Adder Cell with 50% Improvement in Threshold Loss Problem

Authors: T. Vigneswaran, B. Mukundhan, P. Subbarami Reddy

Abstract:

Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. In addition to its main task, which is adding two numbers, it participates in many other useful operations such as subtraction, multiplication, division,, address calculation,..etc. In most of these systems the adder lies in the critical path that determines the overall speed of the system. So enhancing the performance of the 1-bit full adder cell (the building block of the adder) is a significant goal.Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose a new low power adder cell by sacrificing the MOS Transistor count that reduces the serious threshold loss problem, considerably increases the speed and decreases the power when compared to the static energy recovery full (SERF) adder. So a new improved 14T CMOS l-bit full adder cell is presented in this paper. Results show 50% improvement in threshold loss problem, 45% improvement in speed and considerable power consumption over the SERF adder and other different types of adders with comparable performance.

Keywords: Arithmetic circuit, full adder, multiplier, low power, very Large-scale integration (VLSI).

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641 An Improved STBC Structure and Transmission Scheme for High Rate and Reliability in OFDMA Cooperative Communication

Authors: Hyoung-Muk Lim, Won-Jun Choi, Jae-Seon Yoon, Hyoung-Kyu Song

Abstract:

Space-time block code(STBC) has been studied to get full diversity and full rate in multiple input multiple output(MIMO) system. Achieving full rate is difficult in cooperative communications due to the each user consumes the time slots for transmitting information in cooperation phase. So combining MIMO systems with cooperative communications has been researched for full diversity and full rate. In orthogonal frequency division multiple access (OFDMA) system, it is an alternative way that each user shares their allocated subchannels instead of using the MIMO system to improve the transmission rate. In this paper, a Decode-and-forward (DF) based cooperative communication scheme is proposed. The proposed scheme has improved transmission rate and reliability in multi-path fading channel of the OFDMA up-link condition by modified STBC structure and subchannel sharing.

Keywords: cooperation, improved rate, OFDMA, STBC.

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640 A high Speed 8 Transistor Full Adder Design Using Novel 3 Transistor XOR Gates

Authors: Shubhajit Roy Chowdhury, Aritra Banerjee, Aniruddha Roy, Hiranmay Saha

Abstract:

The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three-transistor XOR gate and its performance has been investigated using 0.15um and 0.35um technologies. Compared to the earlier designed 10 transistor full adder, the proposed adder shows a significant improvement in silicon area and power delay product. The whole simulation has been carried out using HSPICE.

Keywords: XOR gate, full adder, improvement in speed, area minimization, transistor count minimization.

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639 Effects of Varying Air Temperature in the Polishing Component of Single-Pass Mill on the Quality of Rice

Authors: M. A. U. Baradi, F. B. Bulao, N. D. Ganotisi, M. Jose C. Regalado, F. P. Bongat, S. B. Manglinong, M. L. O. Quigao, N. G. T. Martinez, R. G. Ancheta, M. P. Ortal

Abstract:

The effects of varying air temperature (full, ¾ full, ½ full aircon adjustment, no aircon) in polishing component of Single-Pass Mill on the quality of Philippine inbred rice variety, was investigated. Parameters measured were milling recovery (MR), headrice recovery (HR), and percentage with bran streaks. Cooling method (with aircon) increased MR, HR, and percentage with bran streaks of milled rice. Highest MR and HR (67.62%; 47.33%) were obtained from ¾ full adjustment whereas no aircon were lowest (66.27%; 39.76%). Temperature in polishing component at ¾ full adjustment was 33oC whereas no aircon was 45oC. There was increase of 1.35% in MR and 7.57% in HR. Additional cost of milling per kg due to aircon cooling was P0.04 at 300 tons/yr volume, with 0.15 yr payback period. Net income was estimated at ₱98,100.00. Percentage of kernels with bran streaks increased from 5%–14%, indicating more nutrients of milled rice.

Keywords: Aircon, air temperature, polishing component, quality, Single-Pass Mill.

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638 A Temperature-Insensitive Wide-Dynamic Range Positive/Negative Full-Wave Rectifier Based on Operational Trasconductance Amplifier using Commercially Available ICs

Authors: C. Chanapromma, T. Worachak, P. Silapan

Abstract:

This paper presents positive and negative full-wave rectifier. The proposed structure is based on OTA using commercially available ICs (LT1228). The features of the proposed circuit are that: it can rectify and amplify voltage signal with controllable output magnitude via input bias current: the output voltage is free from temperature variation. The circuit description merely consists of 1 single ended and 3 fully differential OTAs. The performance of the proposed circuit are investigated though PSpice. They show that the proposed circuit can function as positive/negative full-wave rectifier, where the voltage input wide-dynamic range from -5V to 5V. Furthermore, the output voltage is slightly dependent on the temperature variations.

Keywords: Full-wave rectifier, Positive/negative, OTA, Electronically controllable, Wide-dynamic range

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637 An Efficient Separation for Convolutive Mixtures

Authors: Salah Al-Din I. Badran, Samad Ahmadi, Dylan Menzies, Ismail Shahin

Abstract:

This paper describes a new efficient blind source separation method; in this method we uses a non-uniform filter bank and a new structure with different sub-bands. This method provides a reduced permutation and increased convergence speed comparing to the full-band algorithm. Recently, some structures have been suggested to deal with two problems: reducing permutation and increasing the speed of convergence of the adaptive algorithm for correlated input signals. The permutation problem is avoided with the use of adaptive filters of orders less than the full-band adaptive filter, which operate at a sampling rate lower than the sampling rate of the input signal. The decomposed signals by analysis bank filter are less correlated in each sub-band than the input signal at full-band, and can promote better rates of convergence.

Keywords: Blind source separation (BSS), estimates, full-band, mixtures, Sub-band.

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636 Comparative Growth Rates of Treculia africana Decne: Embryo in Varied Strengths of Murashige and Skoog Basal Medium

Authors: Okafor C. Uche, Agbo P. Ejiofor, Okezie C. Eziuche

Abstract:

This study provides a regeneration protocol for Treculia africana Decne (an endangered plant) through embryo culture. Mature zygotic embryos of T. africana were excised from the seeds aseptically and cultured on varied strengths (full, half and quarter) of Murashige and Skoog (MS) basal medium supplemented. All treatments experienced 100±0.00 percent sprouting except for half and quarter strengths. Plantlets in MS full strength had the highest fresh weight, leaf area, and longest shoot length when compared to other treatments. All explants in full, half, quarter strengths and control had the same number of leaves and sprout rate. Between the treatments, there was a significant difference (P>0.05) in their effect on the length of shoot and root, number of adventitious root, leaf area, and fresh weight. Full strength had the highest mean value in all the above-mentioned parameters and differed significantly (P>0.05) from others except in shoot length, number of adventitious roots, and root length where it did not differ (P<0.05) from half strength. The result of this study indicates that full strength MS basal medium offers a better option for the optimum growth for Treculia africana regeneration in vitro.

Keywords: Medium strengths, Murashige and Skoog, Treculia africana, zygotic embryos.

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635 New VLSI Architecture for Motion Estimation Algorithm

Authors: V. S. K. Reddy, S. Sengupta, Y. M. Latha

Abstract:

This paper presents an efficient VLSI architecture design to achieve real time video processing using Full-Search Block Matching (FSBM) algorithm. The design employs parallel bank architecture with minimum latency, maximum throughput, and full hardware utilization. We use nine parallel processors in our architecture and each controlled by a state machine. State machine control implementation makes the design very simple and cost effective. The design is implemented using VHDL and the programming techniques we incorporated makes the design completely programmable in the sense that the search ranges and the block sizes can be varied to suit any given requirements. The design can operate at frequencies up to 36 MHz and it can function in QCIF and CIF video resolution at 1.46 MHz and 5.86 MHz, respectively.

Keywords: Video Coding, Motion Estimation, Full-Search, Block-Matching, VLSI Architecture.

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634 Application of Flexi-Wall in Noise Barriers Renewal

Authors: B. Daee, H. M. El Naggar

Abstract:

This paper presents an experimental study on structural performance of an innovative noise barrier consisting of poly-block, light polyurethane foam (LPF) and polyurea. This wall system (flexi-wall) is intended to be employed as a vertical extension to existing sound barriers in an accelerated construction method. To aid in the wall design, several mechanical tests were conducted on LPF specimens and two full-scale walls were then fabricated employing the same LPF material. The full-scale walls were subjected to lateral loading in order to establish their lateral resistance. A cyclic fatigue test was also performed on a full-scale flexi-wall in order to evaluate the performance of the wall under a repetitive loading condition. The result of the experiments indicated the suitability of flexi-wall in accelerated construction and confirmed that the structural performance of the wall system under lateral loading is satisfactory for the sound barrier application. The experimental results were discussed and a preliminary design procedure for application of flexi-wall in sound barrier applications was also developed.

Keywords: Noise barrier, Polyurethane Foam, Accelerated construction, Full-scale experiment.

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633 Design and Analysis of a Low Power High Speed 1 Bit Full Adder Cell Based On TSPC Logic with Multi-Threshold CMOS

Authors: Ankit Mitra

Abstract:

An adder is one of the most integral component of a digital system like a digital signal processor or a microprocessor. Being an extremely computationally intensive part of a system, the optimization for speed and power consumption of the adder is of prime importance. In this paper we have designed a 1 bit full adder cell based on dynamic TSPC logic to achieve high speed operation. A high threshold voltage sleep transistor is used to reduce the static power dissipation in standby mode. The circuit is designed and simulated in TSPICE using TSMC 180nm CMOS process. Average power consumption, delay and power-delay product is measured which showed considerable improvement in performance over the existing full adder designs.

Keywords: CMOS, TSPC, MTCMOS, ALU, Clock gating, power gating, pipelining.

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632 Ab initio Study of Co2ZrGe and Co2NbB Full Heusler Compounds

Authors: Abada Ahmed, Hiadsi Said, Ouahrani Tarik, Amrani Bouhalouane, Amara Kadda

Abstract:

Using the first-principles full-potential linearized augmented plane wave plus local orbital (FP-LAPW+lo) method based on density functional theory (DFT), we have investigated the electronic structure and magnetism of full Heusler alloys Co2ZrGe and Co2NbB. These compounds are predicted to be half-metallic ferromagnets (HMFs) with a total magnetic moment of 2.000 B per formula unit, well consistent with the Slater-Pauling rule. Calculations show that both the alloys have an indirect band gaps, in the minority-spin channel of density of states (DOS), with values of 0.58 eV and 0.47 eV for Co2ZrGe and Co2NbB, respectively. Analysis of the DOS and magnetic moments indicates that their magnetism is mainly related to the d-d hybridization between the Co and Zr (or Nb) atoms. The half-metallicity is found to be relatively robust against volume changes. In addition, an atom inside molecule AIM formalism and an electron localization function ELF were also adopted to study the bonding properties of these compounds, building a bridge between their electronic and bonding behavior. As they have a good crystallographic compatibility with the lattice of semiconductors used industrially and negative calculated cohesive energies with considerable absolute values these two alloys could be promising magnetic materials in the spintronic field.

Keywords: Electronic properties, full Heusler alloys, halfmetallic ferromagnets, magnetic properties.

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631 Interconnect Analysis of a Novel Multiplexer Based Full-Adder Cell for Power and Propagation Delay Optimizations

Authors: G.Ramana Murthy, C.Senthilpari, P.Velrajkumar, Lim Tien Sze

Abstract:

The proposed multiplexer-based novel 1-bit full adder cell is schematized by using DSCH2 and its layout is generated by using microwind VLSI CAD tool. The adder cell layout interconnect analysis is performed by using BSIM4 layout analyzer. The adder circuit is compared with other six existing adder circuits for parametric analysis. The proposed adder cell gives better performance than the other existing six adder circuits in terms of power, propagation delay and PDP. The proposed adder circuit is further analyzed for interconnect analysis, which gives better performance than other adder circuits in terms of layout thickness, width and height.

Keywords: Full Adder, Interconnect Analysis, Low-Power, Multiplexer, Propagation Delay, Parametric Analysis.

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630 Design of PI and Fuzzy Controller for High-Efficiency and Tightly Regulated Full Bridge DC-DC Converter

Authors: Sudha Bansal, Lalit Mohan Saini, Dheeraj Joshi

Abstract:

The controller is used to improve the dynamic performance of DC-DC converter by achieving a robust output voltage against load disturbances. This paper presents the performance of PI and Fuzzy controller for a phase- shifted zero-voltage switched full-bridge PWM (ZVS FB- PWM) converters with a closed loop control. The proposed converter is regulated with minimum overshoot and good stability. In this paper phase-shift control method is used as an effective tool to reduce switching losses and duty cycle losses. A 1kW/100KHz dc/dc converter is simulated and analyzed using MATLAB. The circuit is simulated for static and dynamic load (DC motor). It has been observed that performance of converter with fuzzy controller is better than that of PI controller. An efficiency comparison of the converter with a reported topology has also been carried out.

Keywords: Full-bridge converter, phase-shifted, synchronous rectifier (SR), zero-voltage switching (ZVS).

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629 BECOME: Body Experience-Based Co-Operation between Juveniles through Mutually Excited Team Gameplay

Authors: Tsugunosuke Sakai, Haruya Tamaki, Ryuichi Yoshida, Ryohei Egusa, Etsuji Yamaguchi, Shigenori Inagaki, Fusako Kusunoki, Miki Namatame, Masanori Sugimoto, Hiroshi Mizoguchi

Abstract:

We aim to develop a full-body interaction game that could let children cooperate and interact with other children in small groups. As the first step for our aim, the objective of the full-body interaction game developed in this study is to make interaction between children. The game requires two children to jump together with the same timing. We let children experience the game and answer the questionnaires. The children using several strategies to coordinate the timing of their jumps were observed. These included shouting time, watching each other, and jumping in a constant rhythm as if they were skipping rope. In this manner, we observed the children playing the game while cooperating with each other. The results of a questionnaire to evaluate the proposed interactive game indicate that the jumping game was a very enjoyable experience in which the participants could immerse themselves. Therefore, the game enabled children to experience cooperation with others by using body movements.

Keywords: Children, cooperation, full-body interaction game, kinect sensor.

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628 Extending Global Full Orthogonalization method for Solving the Matrix Equation AXB=F

Authors: Fatemeh Panjeh Ali Beik

Abstract:

In the present work, we propose a new method for solving the matrix equation AXB=F . The new method can be considered as a generalized form of the well-known global full orthogonalization method (Gl-FOM) for solving multiple linear systems. Hence, the method will be called extended Gl-FOM (EGl- FOM). For implementing EGl-FOM, generalized forms of block Krylov subspace and global Arnoldi process are presented. Finally, some numerical experiments are given to illustrate the efficiency of our new method.

Keywords: Matrix equations, Iterative methods, Block Krylovsubspace methods.

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627 Active Suspension - Case Study on Robust Control

Authors: Kruczek A., Stříbrský A., Honců J., Hlinovský M.

Abstract:

Automotive suspension system is important part of car comfort and safety. In this article automotive active suspension with linear motor as actuator is designed using H-infinity control. This paper is focused on comparison of different controller designed for quart, half or full-car model (and always used for “full" car). Special attention is placed on energy demand of the whole system. Each controller configuration is simulated and then verified on the hydraulic quarter car test bed.

Keywords: active suspension, linear motor, robust control

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626 Displacement Solution for a Static Vertical Rigid Movement of an Interior Circular Disc in a Transversely Isotropic Tri-Material Full-Space

Authors: D. Mehdizadeh, M. Rahimian, M. Eskandari-Ghadi

Abstract:

This article is concerned with the determination of the static interaction of a vertically loaded rigid circular disc embedded at the interface of a horizontal layer sandwiched in between two different transversely isotropic half-spaces called as tri-material full-space. The axes of symmetry of different regions are assumed to be normal to the horizontal interfaces and parallel to the movement direction. With the use of a potential function method, and by implementing Hankel integral transforms in the radial direction, the government partial differential equation for the solely scalar potential function is transformed to an ordinary 4th order differential equation, and the mixed boundary conditions are transformed into a pair of integral equations called dual integral equations, which can be reduced to a Fredholm integral equation of the second kind, which is solved analytically. Then, the displacements and stresses are given in the form of improper line integrals, which is due to inverse Hankel integral transforms. It is shown that the present solutions are in exact agreement with the existing solutions for a homogeneous full-space with transversely isotropic material. To confirm the accuracy of the numerical evaluation of the integrals involved, the numerical results are compared with the solutions exists for the homogeneous full-space. Then, some different cases with different degrees of material anisotropy are compared to portray the effect of degree of anisotropy.

 

Keywords: Transversely isotropic, rigid disc, elasticity, dual integral equations, tri-material full-space.

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625 Determining Full Stage Creep Properties from Miniature Specimen Creep Test

Authors: W. Sun, W. Wen, J. Lu, A. A. Becker

Abstract:

In this work, methods for determining creep properties which can be used to represent the full life until failure from miniature specimen creep tests based on analytical solutions are presented. Examples used to demonstrate the application of the methods include a miniature rectangular thin beam specimen creep test under three-point bending and a miniature two-material tensile specimen creep test subjected to a steady load. Mathematical expressions for deflection and creep strain rate of the two specimens were presented for the Kachanov-Rabotnov creep damage model. On this basis, an inverse procedure was developed which has potential applications for deriving the full life creep damage constitutive properties from a very small volume of material, in particular, for various microstructure constitutive  regions, e.g. within heat-affected zones of power plant pipe weldments. Further work on validation and improvement of the method is addressed.

Keywords: Creep damage property, analytical solutions, inverse approach, miniature specimen test.

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624 High Level Synthesis of Digital Filters Based On Sub-Token Forwarding

Authors: Iyad F. Jafar, Sandra J. Alrawashdeh, Ban K. Alhamayel

Abstract:

High level synthesis (HLS) is a process which generates register-transfer level design for digital systems from behavioral description. There are many HLS algorithms and commercial tools. However, most of these algorithms consider a behavioral description for the system when a single token is presented to the system. This approach does not exploit extra hardware efficiently, especially in the design of digital filters where common operations may exist between successive tokens. In this paper, we modify the behavioral description to process multiple tokens in parallel. However, this approach is unlike the full processing that requires full hardware replication. It exploits the presence of common operations between successive tokens. The performance of the proposed approach is better than sequential processing and approaches that of full parallel processing as the hardware resources are increased.

Keywords: Digital filters, High level synthesis, Sub-token forwarding

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623 Practical Issues for Real-Time Video Tracking

Authors: Vitaliy Tayanov

Abstract:

In this paper we present the algorithm which allows us to have an object tracking close to real time in Full HD videos. The frame rate (FR) of a video stream is considered to be between 5 and 30 frames per second. The real time track building will be achieved if the algorithm can follow 5 or more frames per second. The principle idea is to use fast algorithms when doing preprocessing to obtain the key points and track them after. The procedure of matching points during assignment is hardly dependent on the number of points. Because of this we have to limit pointed number of points using the most informative of them.

Keywords: video tracking, real-time, Hungarian algorithm, Full HD video.

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