Search results for: drain induced barrier lowering(DIBL).

Authors: Fatemeh Karimi, Morteza Fathipour, Hamdam Ghanatian, Vala Fathipour

Abstract:

In this paper we investigate the electrical characteristics of a new structure of gate all around strained silicon nanowire field effect transistors (FETs) with dual dielectrics by changing the radius (RSiGe) of silicon-germanium (SiGe) wire and gate dielectric. Indeed the effect of high-κ dielectric on Field Induced Barrier Lowering (FIBL) has been studied. Due to the higher electron mobility in tensile strained silicon, the n-type FETs with strained silicon channel have better drain current compare with the pure Si one. In this structure gate dielectric divided in two parts, we have used high-κ dielectric near the source and low-κ dielectric near the drain to reduce the short channel effects. By this structure short channel effects such as FIBL will be reduced indeed by increasing the RSiGe, ID-VD characteristics will be improved. The leakage current and transfer characteristics, the threshold-voltage (Vt), the drain induced barrier height lowering (DIBL), are estimated with respect to, gate bias (VG), RSiGe and different gate dielectrics. For short channel effects, such as DIBL, gate all around strained silicon nanowire FET have similar characteristics with the pure Si one while dual dielectrics can improve short channel effects in this structure.

Keywords: SNWT (silicon nanowire transistor), Tensile Strain, high-κ dielectric, Field Induced Barrier Lowering (FIBL), cylindricalnano wire (CW), drain induced barrier lowering (DIBL).

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Authors: Hung-Pei Hsu, Jyi-Tsong Lin, Po-Hsieh Lin, Cheng-Hsien Chang, Ming-Tsung Shih, Chan-Hsiang Chang, Shih-Chuan Tseng, Min-Yan Lin, Shih-Wen Hsu

Abstract:

In this paper, we propose a novel metal oxide semiconductor field effect transistor with L-shaped channel structure (LMOS), and several type of L-shaped structures are also designed, studied and compared with the conventional MOSFET device for the same average gate length (Lavg). The proposed device electrical characteristics are analyzed and evaluated by three dimension (3-D) ISE-TCAD simulator. It can be confirmed that the LMOS devices have higher on-state drain current and both lower drain-induced barrier lowering (DIBL) and subthreshold swing (S.S.) than its conventional counterpart has. In addition, the transconductance and voltage gain properties of the LMOS are also improved.

Keywords: Average gate length (Lavg), drain-induced barrier lowering (DIBL), L-shaped channel MOSFET (LMOS), subthreshold swing (S.S.).

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Authors: Seyed Abolhasan Naeini, Ali Namaei

Abstract:

This study presents the effect of prefabricated vertical drain system properties on embankment behavior by calculating the settlement, lateral displacement and induced excess pore pressure by numerical method. In order to investigate this behavior, three different prefabricated vertical drains have been simulated under an embankment. The finite element software PLAXIS has been carried out for analyzing the displacements and excess pore pressures. The results showed that the consolidation time and induced excess pore pressure are highly depended to the discharge capacity of the prefabricated vertical drain. The increase in the discharge capacity leads to decrease the consolidation process and the induced excess pore pressure. Moreover, it was seen that the vertical drains spacing does not have any significant effect on the consolidation time. However, the increase in the drains spacing would decrease the system stiffness.

Keywords: Vertical drain, prefabricated, consolidation, embankment.

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Authors: Cheng-Hsien Chang, Jyi-Tsong Lin, Po-Hsieh Lin, Hung-Pei Hsu, Chan-Hsiang Chang, Ming-Tsung Shih, Shih-Chuan Tseng, Min-Yan Lin

Abstract:

In this paper, we have proposed a novel FinFET with extended body under the poly gate, which is called EB-FinFET, and its characteristic is demonstrated by using three-dimensional (3-D) numerical simulation. We have analyzed and compared it with conventional FinFET. The extended body height dependence on the drain induced barrier lowering (DIBL) and subthreshold swing (S.S) have been also investigated. According to the 3-D numerical simulation, the proposed structure has a firm structure, an acceptable short channel effect (SCE), a reduced series resistance, an increased on state drain current (I on) and a large normalized I DS. Furthermore, the structure can also improve corner effect and reduce self-heating effect due to the extended body. Our results show that the EBFinFET is excellent for nanoscale device.

Keywords: SOI, FinFET, tri-gate, self-heating effect.

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Authors: M. Khaouani, A. Guen-Bouazza, B. Bouazza, Z. Kourdi

Abstract:

The integrity and issues related to electrostatic performance associated with scaling Si MOSFET bulk sub 10nm channel length promotes research in new device architectures such as SOI, double gate and GAA MOSFET. In this paper, we present some novel characteristic of horizontal rectangular gate\gate all around MOSFETs with dual metal of gate we obtained using SILVACO TCAD tools. We will also exhibit some simulation results we obtained relating to the influence of some parameters variation on our structure, that having a direct impact on their threshold voltage and drain current. In addition, our TFET showed reasonable I_ON/I_OFF ratio of (10⁴) and low drain induced barrier lowering (DIBL) of 39 mV/V.

Keywords: GAA, SILVACO, QUANTUM, MOSFETs.

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Authors: Muhammad Wajid Tahir, Rubina Kauser, Majid Ali Tahir

Abstract:

Pakistani doctors (MBBS) are emigrating towards developed countries for professional adjustments. This study aims to highlight causes and consequences of doctors- brain drain from Pakistan. Primary data was collected from Mayo Hospital, Lahore by interviewing doctors (n=100) through systematic random sampling technique. It found that various socio-economic and political conditions are working as push and pull factors for brain drain of doctors in Pakistan. Majority of doctors (83%) declared poor remunerations and professional infrastructure of health department as push factor of doctors- brain drain. 81% claimed that continuous instability in political situation and threats of terrorism are responsible for emigration of doctors. 84% respondents considered fewer opportunities of further studies responsible for their emigration. Brain drain of doctors is affecting health sector-s policies / programs, standard doctor-patient ratios and quality of health services badly.

Keywords: Brain Drain, Emigration, Remuneration, Politicalinstability, MBBS doctors

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Authors: E. Yosry, W. Fikry, A. El-henawy, M. Marzouk

Abstract:

This work offers a study of new simple compact model of dual-drain Magnetic Field Effect Transistor (MAGFET) including geometrical effects and biasing dependency. An explanation of the sensitivity is investigated, involving carrier deflection as the dominant operating principle. Finally, model verification with simulation results is introduced to ensure that acceptable error of 2% is achieved.

Keywords: MAGFET, Modeling, Simulation, Split-drain.

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Authors: K. Al-Heuseen, M. R. Hashim

Abstract:

The current-voltage (I-V) characteristics of Pd/n-GaN Schottky barrier were studied at temperatures over room temperature (300-470K). The values of ideality factor (n), zero-bias barrier height (φB0), flat barrier height (φBF) and series resistance (Rs) obtained from I-V-T measurements were found to be strongly temperature dependent while (φBo) increase, (n), (φBF) and (Rs) decrease with increasing temperature. The apparent Richardson constant was found to be 2.1x10-9 Acm-2K-2 and mean barrier height of 0.19 eV. After barrier height inhomogeneities correction, by assuming a Gaussian distribution (GD) of the barrier heights, the Richardson constant and the mean barrier height were obtained as 23 Acm-2K-2 and 1.78eV, respectively. The corrected Richardson constant was very closer to theoretical value of 26 Acm-2K-2. 

Keywords: Electrical properties, Gaussian distribution, Pd-GaN Schottky diodes, thermionic emission.

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Authors: N. Shen, T. T. Le, H. Y. Yu, Z. X. Chen, K. T. Win, N. Singh, G. Q. Lo, D. -L. Kwong

Abstract:

In this paper, we present a vertical nanowire thin film transistor with gate-all-around architecture, fabricated using CMOS compatible processes. A novel method of fabricating polysilicon vertical nanowires of diameter as small as 30 nm using wet-etch is presented. Both n-type and p-type vertical poly-silicon nanowire transistors exhibit superior electrical characteristics as compared to planar devices. On a poly-crystalline nanowire of 30 nm diameter, high Ion/Ioff ratio of 106, low drain-induced barrier lowering (DIBL) of 50 mV/V, and low sub-threshold slope SS~100mV/dec are demonstrated for a device with channel length of 100 nm.

Keywords: Nanowire (NW), Gate-all-around (GAA), polysilicon (poly-Si), thin-film transistor (TFT).

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Authors: Muhibul Haque Bhuyan, Quazi D. M. Khosru

Abstract:

Carrier scatterings in the inversion channel of MOSFET dominates the carrier mobility and hence drain current. This paper presents an analytical model of the subthreshold drain current incorporating the effective electron mobility model of the pocket implanted nano scale n-MOSFET. The model is developed by assuming two linear pocket profiles at the source and drain edges at the surface and by using the conventional drift-diffusion equation. Effective electron mobility model includes three scattering mechanisms, such as, Coulomb, phonon and surface roughness scatterings as well as ballistic phenomena in the pocket implanted n-MOSFET. The model is simulated for various pocket profile and device parameters as well as for various bias conditions. Simulation results show that the subthreshold drain current data matches the experimental data already published in the literature.

Keywords: Linear Pocket Profile, Pocket Implanted n-MOSFET, Subthreshold Drain Current and Effective Mobility Model.

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Authors: A. Hamdoune, M. Abdelmoumene, A. Hamroun

Abstract:

The objective of this paper is to simulate static I-V and dynamic characteristics of an appropriated and recessed n-GaN/AlxGa1-xN/GaN high electron mobility (HEMT). Using SILVACO TCAD device simulation, and optimized technological parameters; we calculate the drain-source current (lDS) as a function of the drain-source voltage (VDS) for different values ​​of the gate-source voltage (VGS), and the drain-source current (lDS) depending on the gate-source voltage (VGS) for a drain-source voltage (VDS) of 20 V, for various temperatures. Then, we calculate the cut-off frequency and the maximum oscillation frequency for different temperatures.

We obtain a high drain-current equal to 60 mA, a low knee voltage (Vknee) of 2 V, a high pinch-off voltage (VGS0) of 53.5 V, a transconductance greater than 600 mS/mm, a cut-off frequency (f_T) of about 330 GHz, and a maximum oscillation frequency (fmax) of about 1 THz.

Keywords: n-GaN/AlGaN/GaN HEMT, drain-source current (IDS), transconductance (gm), cut-off frequency (fT), maximum oscillation frequency (fmax).

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Authors: I. Sahul Hamid, Abraham V. M.

Abstract:

A decomposition of a graph G is a collection ψ of subgraphs H1,H2, . . . , Hr of G such that every edge of G belongs to exactly one Hi. If each Hi is either an induced path or an induced cycle in G, then ψ is called an induced path decomposition of G. The minimum cardinality of an induced path decomposition of G is called the induced path decomposition number of G and is denoted by πi(G). In this paper we initiate a study of this parameter.

Keywords: Path decomposition, Induced path decomposition, Induced path decomposition number.

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Authors: Somayeh Gholami, Meysam Khakbaz

Abstract:

The current-voltage characteristics of a PtSi/p-Si Schottky barrier diode was measured at the temperature of 85 K and from the forward bias region of the I-V curve, the electrical parameters of the diode were measured by three methods. The results obtained from the two methods which considered the series resistance were in close agreement with each other and from them barrier height (
), ideality factor (n) and series resistance () were found to be 0.2045 eV, 2.877 and 14.556 K
respectively. By measuring the I-V characteristics in the temperature range of 85-136 K the electrical parameters were observed to have strong dependency on temperature. The increase of barrier height and decrease of ideality factor with increasing temperature is attributed to the existence of barrier height inhomogeneities in the silicide-semiconductor structure.

Keywords: Schottky diode, barrier height, series resistance, I-V, barrier height inhomogeneities.

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Authors: K. Ratan Singh, P. K. Das

Abstract:

An induced graphoidal cover of a graph G is a collection ψ of (not necessarily open) paths in G such that every path in ψ has at least two vertices, every vertex of G is an internal vertex of at most one path in ψ, every edge of G is in exactly one path in ψ and every member of ψ is an induced cycle or an induced path. The minimum cardinality of an induced graphoidal cover of G is called the induced graphoidal covering number of G and is denoted by ηi(G) or ηi. Here we find induced graphoidal cover for some classes of graphs.

Keywords: Graphoidal cover, Induced graphoidal cover, Induced graphoidal covering number.

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Authors: Salam Khalid Al-Agha, Inamullah Bhatti, Hossam Adel Zaqoot, Shaukat Hayat Khan, Abdul Khalique Ansari

Abstract:

This paper presents the results of preliminary assessment of water quality along the coastal areas in the vicinity of Left Bank Outfall Drainage (LBOD) and Tidal Link Drain (TLD) in Sindh province after the cyclone 2A occurred in 1999. The water samples were collected from various RDs of Tidal Link Drain and lakes during September 2001 to April 2002 and were analysed for salinity, nitrite, phosphate, ammonia, silicate and suspended material in water. The results of the study showed considerable variations in water quality depending upon the location along the coast in the vicinity of LBOD and RDs. The salinity ranged between 4.39–65.25 ppt in Tidal Link Drain samples whereas 2.4–38.05 ppt in samples collected from lakes. The values of suspended material at various RDs of Tidal Link Drain ranged between 56.6–2134 ppm and at the lakes between 68–297 ppm. The data of continuous monitoring at RD–93 showed the range of PO4 (8.6–25.2 μg/l), SiO3 (554.96–1462 μg/l), NO2 (0.557.2–25.2 μg/l) and NH3 (9.38–23.62 μg/l). The concentration of nutrients in water samples collected from different RDs was found in the range of PO4 (10.85 to 11.47 μg/l), SiO3 (1624 to 2635.08 μg/l), NO2 (20.38 to 44.8 μg/l) and NH3 (24.08 to 26.6 μg/l). Sindh coastal areas which situated at the north-western boundary the Arabian Sea are highly vulnerable to flood damages due to flash floods during SW monsoon or impact of sea level rise and storm surges coupled with cyclones passing through Arabian Sea along Pakistan coast. It is hoped that the obtained data in this study would act as a database for future investigations and monitoring of LBOD and Tidal Link Drain coastal waters.

Keywords: Tidal Link Drain, Salinity, Nutrients, Nitrite salts, Coastal areas.

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Authors: Abraham V. M., I. Sahul Hamid

Abstract:

A decomposition of a graph G is a collection ψ of graphs H1,H2, . . . , Hr of G such that every edge of G belongs to exactly one Hi. If each Hi is either an induced path in G, then ψ is called an induced acyclic path decomposition of G and if each Hi is a (induced) cycle in G then ψ is called a (induced) cycle decomposition of G. The minimum cardinality of an induced acyclic path decomposition of G is called the induced acyclic path decomposition number of G and is denoted by ¤Çia(G). Similarly the cyclic decomposition number ¤Çc(G) is defined. In this paper we begin an investigation of these parameters.

Keywords: Cycle decomposition, Induced acyclic path decomposition, Induced acyclic path decomposition number.

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Authors: Ahmed Shariful Alam, Abu Hena M. Mustafa Kamal, M. Abdul Rahman, M. Nasmus Sakib Khan Shabbir, Atiqul Islam

Abstract:

According to the rules of quantum mechanics there is a non-vanishing probability of for an electron to tunnel through a thin insulating barrier or a thin capacitor which is not possible according to the laws of classical physics. Tunneling of electron through a thin insulating barrier or tunnel junction is a random event and the magnitude of current flowing due to the tunneling of electron is very low. As the current flowing through a Single Electron Transistor (SET) is the result of electron tunneling through tunnel junctions of its source and drain the supply voltage requirement is also very low. As a result, the power consumption across a Single Electron Transistor is ultra-low in comparison to that of a MOSFET. In this paper simulations have been done with PSPICE for an inverter built with both SETs and MOSFETs. 35mV supply voltage was used for a SET built inverter circuit and the supply voltage used for a CMOS inverter was 3.5V.

Keywords: ITRS, enhancement type MOSFET, island, DC analysis, transient analysis, power consumption, background charge co-tunneling.

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Authors: R. Osada, S. Ogata, T. Segawa

Abstract:

Dielectric barrier discharge plasma actuators (DBD-PAs) have been developed for active flow control devices. However, it is necessary to reduce ozone produced by DBD toward practical applications using DBD-PAs. In this study, variations of ozone concentration, flow velocity, power consumption were investigated by changing exposed electrodes of DBD-PAs. Two exposed electrode prototypes were prepared: span-type with exposed electrode width of 0.1 mm, and normal-type with width of 5 mm. It was found that span-type shows lower power consumption and higher flow velocity than that of normal-type at V_p-p = 4.0-6.0 kV. Ozone concentration of span-type higher than normal-type at V_p-p = 4.0-8.0 kV. In addition, it was confirmed that catalyst located in downstream from the exposed electrode can reduce ozone concentration between 18 and 42% without affecting the induced flow.

Keywords: Dielectric barrier discharge plasma actuators, ozone diffusion, PIV measurement, power consumption.

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Authors: K. Ratan Singh, P. K. Das

Abstract:

An induced acyclic graphoidal cover of a graph G is a collection ψ of open paths in G such that every path in ψ has atleast two vertices, every vertex of G is an internal vertex of at most one path in ψ, every edge of G is in exactly one path in ψ and every member of ψ is an induced path. The minimum cardinality of an induced acyclic graphoidal cover of G is called the induced acyclic graphoidal covering number of G and is denoted by ηia(G) or ηia. Here we find induced acyclic graphoidal cover for some classes of graphs.

Keywords: Graphoidal cover, Induced acyclic graphoidal cover, Induced acyclic graphoidal covering number.

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Authors: Dawit Burusie Abdi, Mamidala Jagadesh Kumar

Abstract:

In this paper, using 2D TCAD simulations, the application of a dual material gate (DMG) for suppressing ambipolar conduction in a tunnel field effect transistor (TFET) is demonstrated. Using the proposed DMG concept, the ambipolar conduction can be effectively suppressed even if the drain doping is as high as that of the source doping. Achieving this symmetrical doping, without the ambipolar conduction in TFETs, gives the advantage of realizing both n-type and p-type devices with the same doping sequences. Furthermore, the output characteristics of the DMG TFET exhibit a good saturation when compared to that of the gate-drain underlap approach. This improved behavior of the DMG TFET makes it a good candidate for inverter based logic circuits.

Keywords: Dual material gate, suppressing ambipolar current, symmetrically doped TFET, tunnel FETs, PNPN TFET.

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Authors: Fatemeh Karimi, Morteza Fathipour, Hamdam Ghanatian, Vala Fathipour

Abstract:

In this paper electrical characteristics of various kinds of multiple-gate silicon nanowire transistors (SNWT) with the channel length equal to 7 nm are compared. A fully ballistic quantum mechanical transport approach based on NEGF was employed to analyses electrical characteristics of rectangular and cylindrical silicon nanowire transistors as well as a Double gate MOS FET. A double gate, triple gate, and gate all around nano wires were studied to investigate the impact of increasing the number of gates on the control of the short channel effect which is important in nanoscale devices. Also in the case of triple gate rectangular SNWT inserting extra gates on the bottom of device can improve the application of device. The results indicate that by using gate all around structures short channel effects such as DIBL, subthreshold swing and delay reduces.

Keywords: SNWT (silicon nanowire transistor), non equilibriumGreen's function (NEGF), double gate (DG), triple gate (TG), multiple gate, cylindrical nano wire (CW), rectangular nano wire(RW), Poisson_ Schrödinger solver, drain induced barrier lowering(DIBL).

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Authors: Muhibul Haque Bhuyan, Quazi D. M. Khosru

Abstract:

Carriers scattering in the inversion channel of n- MOSFET dominates the drain current. This paper presents an effective electron mobility model for the pocket implanted nano scale n-MOSFET. The model is developed by using two linear pocket profiles at the source and drain edges. The channel is divided into three regions at source, drain and central part of the channel region. The total number of inversion layer charges is found for these three regions by numerical integration from source to drain ends and the number of depletion layer charges is found by using the effective doping concentration including pocket doping effects. These two charges are then used to find the effective normal electric field, which is used to find the effective mobility model incorporating the three scattering mechanisms, such as, Coulomb, phonon and surface roughness scatterings as well as the ballistic phenomena for the pocket implanted nano-scale n-MOSFET. The simulation results show that the derived mobility model produces the same results as found in the literatures.

Keywords: Linear Pocket Profile, Pocket Implanted n-MOSFET, Effective Electric Field and Effective Mobility Model.

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Authors: Hiroyuki Nishida, Taku Nonomura, Takashi Abe

Abstract:

Wall-surface jet induced by the dielectric barrier discharge (DBD) has been proposed as an actuator for active flow control in aerodynamic applications. Discharge plasma evolution of the DBD plasma actuator was simulated based on a simple fluid model, in which the electron, one type of positive ion and negative ion were taken into account. Two-dimensional simulation was conducted, and the results are in agreement with the insights obtained from experimental studies. The simulation results indicate that the discharge mode changes depending on applied voltage slope; when the applied voltage is positive-going with high applied voltage slope, the corona-type discharge mode turns into the streamer-type discharge mode and the threshold voltage slope is around 300 kV/ms in this simulation. The characteristics of the electrohydrodynamic (EHD) force, which is the source of the wall-surface jet, also change depending on the discharge mode; the tentative peak value of the EHD force during the positive-going voltage phase is saturated by the periodical formation of the streamer-type discharge.

Keywords: Dielectric barrier discharge, Plasma actuator, Fluid simulation.

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Authors: Hakim Aguedal, Hafida Hentit, Abdallah Aziz, Djillali Rida Merouani, Abdelkader Iddou

Abstract:

The major environmental risk of soil pollution is the contamination of groundwater by infiltration of organic and inorganic pollutants which can cause a serious menace. To prevent this risk and to protect the groundwater, we proceeded in this study to test the reliability of a biosolid as barrier to prevent the migration of very dangerous pollutants as ‘Cadmium’ through the different soil layers. In this study, we tried to highlight the effect of several parameters such as: turbidity (different cycle of Hydration/Dehydration), rainfall, effect of initial Cd(II) concentration and the type of soil. These parameters allow us to find the most effective manner to integrate this barrier in the soil. From the results obtained, we found a significant effect of the barrier. Indeed, the recorded passing quantities are lowest for the highest rainfall; we noted also that the barrier has a better affinity towards higher concentrations; the most retained amounts of cadmium has been in the top layer of the two types of soil tested, while the lowest amounts of cadmium are recorded in the bottom layers of soils.

Keywords: Adsorption of Cadmium, Barrier, Groundwater Pollution, Protection.

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Authors: Shiyang Zhu, Guo-Qiang Lo, Dim-Lee Kwong

Abstract:

We prove detailed analysis of a waveguide-based Schottky barrier photodetector (SBPD) where a thin silicide film is put on the top of a silicon-on-insulator (SOI) channel waveguide to absorb light propagating along the waveguide. Taking both the confinement factor of light absorption and the wall scanning induced gain of the photoexcited carriers into account, an optimized silicide thickness is extracted to maximize the effective gain, thereby the responsivity. For typical lengths of the thin silicide film (10-20 Ðçm), the optimized thickness is estimated to be in the range of 1-2 nm, and only about 50-80% light power is absorbed to reach the maximum responsivity. Resonant waveguide-based SBPDs are proposed, which consist of a microloop, microdisc, or microring waveguide structure to allow light multiply propagating along the circular Si waveguide beneath the thin silicide film. Simulation results suggest that such resonant waveguide-based SBPDs have much higher repsonsivity at the resonant wavelengths as compared to the straight waveguidebased detectors. Some experimental results about Si waveguide-based SBPD are also reported.

Keywords: Infrared detector, Schottky-barrier, Silicon waveguide, Silicon photonics

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Authors: Paniz Tafakori, Ali A. Orouji

Abstract:

In this paper the features of multiple material gate silicon-on-insulator MOSFETs are presented and compared with single material gate silicon-on-insulator MOSFET structures. The results indicate that the multiple material gate structures reduce short channel effects such as drain induce barrier lowering, hot electron effect and better current characteristics in comparison with single material structures

Keywords: Short-channel effects (SCEs), Dual material gate (DMG), Triple material gate (TMG), Pentamerous material gate (PMG).

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Authors: C. Papapicco

Abstract:

Motherhood is an existential human relationship that lasts for the whole life and is always interwoven with subjectivity and culture. As a result of the brain drain, the motherhood becomes motherhood at distance. Starting from the hypothesis that re-signification of the mother at distance practices is culturally relevant; the research aims to understand the experience of mother at a distance in order to extrapolate the strategies of management of the empty nest. Specifically, the research aims to evaluate the experience of a brain drain’s mother, who created a blog that intends to take care of other parents at a distance. Actually, the blog is the only artifact symbol of the Italian culture of motherhood at distance. In the research, a Netnographic Analysis of the blog mammedicervelliinfuga.com is offered with the aim of understanding if the online world becomes an opportunity to manage the role of mother at a distance. A narrative interview with the blog creator was conducted and then the texts were analyzed by means of a Diatextual Analysis approach. It emerged that the migration projects of talented children take on different meanings and representations for parents. Thus, it is shown that the blog becomes a new form of understanding and practicing motherhood at a distance.

Keywords: Brain drain, diatextual analysis, distance motherhood blog, online and offline narrations.

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Authors: Priyanka Malik A, Rishu Chaujar B, Mridula Gupta C, R.S. Gupta D

Abstract:

In this paper, for the first time, a two-dimensional (2D) analytical drain current model for sub-100 nm multi-layered gate material engineered trapezoidal recessed channel (MLGMETRC) MOSFET: a novel design is presented and investigated using ATLAS and DEVEDIT device simulators, to mitigate the large gate leakages and increased standby power consumption that arise due to continued scaling of SiO2-based gate dielectrics. The twodimensional (2D) analytical model based on solution of Poisson-s equation in cylindrical coordinates, utilizing the cylindrical approximation, has been developed which evaluate the surface potential, electric field, drain current, switching metric: ION/IOFF ratio and transconductance for the proposed design. A good agreement between the model predictions and device simulation results is obtained, verifying the accuracy of the proposed analytical model.

Keywords: ATLAS, DEVEDIT, NJD, MLGME- TRCMOSFET.

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Authors: Ashwani K. Rana, Narottam Chand, Vinod Kapoor

Abstract:

In this paper, gate leakage current has been mitigated by the use of novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure for the first time. A compact analytical model has been developed to study the gate leakage behaviour of proposed MOSFET structure. The result obtained has found good agreement with the Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. It is found that optimal Source/Drain-to-Gate Non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and DIBL characteristic. It is concluded that this structure solves the problem of high leakage current without introducing the extra series resistance.

Keywords: Gate tunneling current, analytical model, spacer dielectrics, DIBL, subthreshold slope.

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Authors: Gu Wei, Gao Wei

Abstract:

In this report, an OTA which is used in fully differential pipelined ADC was described. Using gain-boost architecture with difference-ended amplifier, this OTA achieve high-gain and high-speed. Besides, the CMFB circuit is also used, and some methods are concerned to improve the performance. Then, by optimization the layout design, OTA-s mismatch was reduced. This design was using TSMC 0.18um CMOS process and simulation both schematic and layout in Cadence. The result of the simulation shows that the OTA has a gain up to 80dB,a unity gain bandwidth of about 1.437GHz for a 2pF load, a slew rate is about 428V/μs, a output swing is 0.2V~1.35V, with the power supply of 1.8V, the power consumption is 88mW. This amplifier was used in a 10bit 150MHz pipelined ADC.

Keywords: OTA, common drain, CMFB, pipelined ADC

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