Analytical Subthreshold Drain Current Model Incorporating Inversion Layer Effective Mobility Model for Pocket Implanted Nano Scale n-MOSFET

Authors: Muhibul Haque Bhuyan, Quazi D. M. Khosru

Abstract:

Carrier scatterings in the inversion channel of MOSFET dominates the carrier mobility and hence drain current. This paper presents an analytical model of the subthreshold drain current incorporating the effective electron mobility model of the pocket implanted nano scale n-MOSFET. The model is developed by assuming two linear pocket profiles at the source and drain edges at the surface and by using the conventional drift-diffusion equation. Effective electron mobility model includes three scattering mechanisms, such as, Coulomb, phonon and surface roughness scatterings as well as ballistic phenomena in the pocket implanted n-MOSFET. The model is simulated for various pocket profile and device parameters as well as for various bias conditions. Simulation results show that the subthreshold drain current data matches the experimental data already published in the literature.

Keywords: Linear Pocket Profile, Pocket Implanted n-MOSFET, Subthreshold Drain Current and Effective Mobility Model.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1336468

References:

[1] S. M. Sze, "Physics of Semiconductor Devices,” 2nd Edition, John Wiley and Sons, New York, ch. 8, 1981.
[2] M. Orlowski, C. Mazure and F. Lau, "Submicron short channel effects due to gate reoxidation induced lateral interstitial diffusion,” IEEE IEDM Technical Digest, p. 632, 1987.
[3] M. Nishida and H. Onodera, "An anomalous increase of threshold voltage with shortening the channel lengths for deeply boron-implanted n-channel MOSFETs,” IEEE Trans. on Electron Devices, vol. 48, pp. 1101, 1981.
[4] K. Y. Lim and X. Zhou, "Modeling of Threshold Voltage with Nonuniform Substrate Doping,” in Proc. of the IEEE International Conference on Semiconductor Electronics (ICSE 1998), Malaysia, pp. 27-31, 1998.
[5] B. Yu, H. Wang, O. Millic, Q. Xiang, W. Wang, J. X. An and M. R. Lin, "50 nm gate length CMOS transistor with super-halo: Design, process and reliability,” IEDM Technical Digest, pp. 653-656, 1999.
[6] K. M. Cao, W. Liu, X. Jin, K. Vasant, K. Green, J. Krick, T. Vrotsos and C. Hu, "Modeling of pocket implanted MOSFETs for anomalous analog behavior,” IEEE IEDM Technical Digest, pp. 171-174, 1999.
[7] Y. S. Pang and J. R. Brews, "Models for subthreshold and above subthreshold currents in 0.1 μm pocket n-MOSFETs for low voltage applications,” IEEE Transactions on Electron Devices, vol. 49, pp. 832-839, May 2002.
[8] B. Yu, C. H. Wann, E. D. Nowak, K. Noda and C. Hu, "Short Channel Effect improved by lateral channel engineering in deep-submicrometer MOSFETs,” IEEE Transactions on Electron Devices, vol. 44, pp. 627-633, April 1997.
[9] M. H. Bhuyan and Q. D. M. Khosru, ”Linear Pocket Profile Based Threshold Voltage Model for Sub-100 nm n-MOSFET,” International Journal of Electrical and Computer Engineering, vol. 5, no. 5, pp. 310-315, May 2010.
[10] P. Klein and S. Chladek, "A New Mobility Model for Pocket Implanted Quarter Micron n-MOSFETs and Below,” IEEE IEDM Technical Digest, pp. 1587-1590, 2001.
[11] H. S. Shin, C. Lee, S. W. Hwang, B. G. Park and H. S. Min, "Channel length independent subthreshold characteristics in submicron MOSFETs,” IEEE Electron Device Letters, vol. 19, pp. 137-139, Apr. 1998.
[12] C. S. Ho, J. J. Liou, K.-Y. Huang and C.-C. Cheng, "An analytical subthreshold current model for pocket implanted NMOSFETs,” IEEE Transactions on Electron Devices, vol. 50, no. 6, pp. 1475-1479, Jun. 2003.
[13] R. J. E. Hueting and A. Heringa, "Analysis of the Subthreshold Current of Pocket or Halo-Implanted nMOSFETs,” IEEE Transactions on Electron Devices, vol. 53, no. 7, pp. 1641-1646, Jul. 2006.
[14] M. H. Bhuyan and Q. D. M. Khosru, "An analytical subthreshold drain current model for pocket implanted nano scale n-MOSFET,” Journal of Electron Devices, ISSN 1682-3427, vol. 8, pp 263-267, October 2010.
[15] S. Takagi, A. Toriumi, M. Iwase, and H. Tango, "On the University of Inversion Layer Mobility in Si MOSFET’s: Part I-Effects of Surface Impurity Concentration,” IEEE Transactions on Electron Devices, vol. 41, pp. 2357-2362, 1994.
[16] B. Lemaitre, "An improved analytical LDD-MOSFET model for digital and analog circuit simulation for all channel length down to deepsubmicron,” IEEE IEDM Technical Digest, 1991.
[17] R. M. D. A. Velghe, D. B. M. Klaassen and F. M. Klaassen, "Compact MOS modeling for analog circuit simulation,” IEEE IEDM Technical Digest, pp. 485-488, 1993.
[18] Y. Cheng et. al., BSIM3v3 Manual, University of California, 1996.
[19] Y. P. Tsividis, "Operation and Modeling of the MOS Transistor,” New York, McGraw-Hill, 1999.
[20] A. G. Sabnis and J. T. Clemens, "Characterization of the electron mobility in the inverted <100> Si,” IEEE IEDM Technical Digest, 1979, pp. 18-21.
[21] S. Villa, A. L. Lacaita, L. M. Perron and R. Bez, "A Physically-Based Model of the Effective Mobility in Heavily-Doped n-MOSFETs,” IEEE Transactions on Electron Devices, vol. 45, no. 1, pp. 110-115, 1998.
[22] M. H. Bhuyan and Q. D. M. Khosru, "Linear profile based analytical surface potential model for pocket implanted sub-100 nm n-MOSFET,” Journal of Electron Devices, ISSN 1682-3427, vol. 7, pp 235-240, April 2010.
[23] M. H. Bhuyan and Q. D. M. Khosru, ”Inversion Layer Effective Mobility Model for Pocket Implanted Nano Scale n-MOSFET,” International Journal of Electrical and Electronics Engineering, vol. 5, no. 1, pp. 50-57, July 2011.
[24] N. Arora, "MOSFET models for VLSI circuit simulation: theory and practice,” Springer Link-Verlag, New York, USA, 1993.
[25] T. A. Fieldly and M. Shur, "Threshold voltage modeling and the subthreshold operation of short-channel MOSFETs,” IEEE Transactions on Electron Devices, vol. 40, pp. 137, Jan. 1993.