Search results for: common drain

Authors: Gu Wei, Gao Wei

Abstract:

In this report, an OTA which is used in fully differential pipelined ADC was described. Using gain-boost architecture with difference-ended amplifier, this OTA achieve high-gain and high-speed. Besides, the CMFB circuit is also used, and some methods are concerned to improve the performance. Then, by optimization the layout design, OTA-s mismatch was reduced. This design was using TSMC 0.18um CMOS process and simulation both schematic and layout in Cadence. The result of the simulation shows that the OTA has a gain up to 80dB,a unity gain bandwidth of about 1.437GHz for a 2pF load, a slew rate is about 428V/μs, a output swing is 0.2V~1.35V, with the power supply of 1.8V, the power consumption is 88mW. This amplifier was used in a 10bit 150MHz pipelined ADC.

Keywords: OTA, common drain, CMFB, pipelined ADC

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Authors: Muhammad Wajid Tahir, Rubina Kauser, Majid Ali Tahir

Abstract:

Pakistani doctors (MBBS) are emigrating towards developed countries for professional adjustments. This study aims to highlight causes and consequences of doctors- brain drain from Pakistan. Primary data was collected from Mayo Hospital, Lahore by interviewing doctors (n=100) through systematic random sampling technique. It found that various socio-economic and political conditions are working as push and pull factors for brain drain of doctors in Pakistan. Majority of doctors (83%) declared poor remunerations and professional infrastructure of health department as push factor of doctors- brain drain. 81% claimed that continuous instability in political situation and threats of terrorism are responsible for emigration of doctors. 84% respondents considered fewer opportunities of further studies responsible for their emigration. Brain drain of doctors is affecting health sector-s policies / programs, standard doctor-patient ratios and quality of health services badly.

Keywords: Brain Drain, Emigration, Remuneration, Politicalinstability, MBBS doctors

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Authors: E. Yosry, W. Fikry, A. El-henawy, M. Marzouk

Abstract:

This work offers a study of new simple compact model of dual-drain Magnetic Field Effect Transistor (MAGFET) including geometrical effects and biasing dependency. An explanation of the sensitivity is investigated, involving carrier deflection as the dominant operating principle. Finally, model verification with simulation results is introduced to ensure that acceptable error of 2% is achieved.

Keywords: MAGFET, Modeling, Simulation, Split-drain.

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Authors: Muhibul Haque Bhuyan, Quazi D. M. Khosru

Abstract:

Carrier scatterings in the inversion channel of MOSFET dominates the carrier mobility and hence drain current. This paper presents an analytical model of the subthreshold drain current incorporating the effective electron mobility model of the pocket implanted nano scale n-MOSFET. The model is developed by assuming two linear pocket profiles at the source and drain edges at the surface and by using the conventional drift-diffusion equation. Effective electron mobility model includes three scattering mechanisms, such as, Coulomb, phonon and surface roughness scatterings as well as ballistic phenomena in the pocket implanted n-MOSFET. The model is simulated for various pocket profile and device parameters as well as for various bias conditions. Simulation results show that the subthreshold drain current data matches the experimental data already published in the literature.

Keywords: Linear Pocket Profile, Pocket Implanted n-MOSFET, Subthreshold Drain Current and Effective Mobility Model.

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Authors: A. Hamdoune, M. Abdelmoumene, A. Hamroun

Abstract:

The objective of this paper is to simulate static I-V and dynamic characteristics of an appropriated and recessed n-GaN/AlxGa1-xN/GaN high electron mobility (HEMT). Using SILVACO TCAD device simulation, and optimized technological parameters; we calculate the drain-source current (lDS) as a function of the drain-source voltage (VDS) for different values ​​of the gate-source voltage (VGS), and the drain-source current (lDS) depending on the gate-source voltage (VGS) for a drain-source voltage (VDS) of 20 V, for various temperatures. Then, we calculate the cut-off frequency and the maximum oscillation frequency for different temperatures.

We obtain a high drain-current equal to 60 mA, a low knee voltage (Vknee) of 2 V, a high pinch-off voltage (VGS0) of 53.5 V, a transconductance greater than 600 mS/mm, a cut-off frequency (f_T) of about 330 GHz, and a maximum oscillation frequency (fmax) of about 1 THz.

Keywords: n-GaN/AlGaN/GaN HEMT, drain-source current (IDS), transconductance (gm), cut-off frequency (fT), maximum oscillation frequency (fmax).

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Authors: Seyed Abolhasan Naeini, Ali Namaei

Abstract:

This study presents the effect of prefabricated vertical drain system properties on embankment behavior by calculating the settlement, lateral displacement and induced excess pore pressure by numerical method. In order to investigate this behavior, three different prefabricated vertical drains have been simulated under an embankment. The finite element software PLAXIS has been carried out for analyzing the displacements and excess pore pressures. The results showed that the consolidation time and induced excess pore pressure are highly depended to the discharge capacity of the prefabricated vertical drain. The increase in the discharge capacity leads to decrease the consolidation process and the induced excess pore pressure. Moreover, it was seen that the vertical drains spacing does not have any significant effect on the consolidation time. However, the increase in the drains spacing would decrease the system stiffness.

Keywords: Vertical drain, prefabricated, consolidation, embankment.

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Authors: Salam Khalid Al-Agha, Inamullah Bhatti, Hossam Adel Zaqoot, Shaukat Hayat Khan, Abdul Khalique Ansari

Abstract:

This paper presents the results of preliminary assessment of water quality along the coastal areas in the vicinity of Left Bank Outfall Drainage (LBOD) and Tidal Link Drain (TLD) in Sindh province after the cyclone 2A occurred in 1999. The water samples were collected from various RDs of Tidal Link Drain and lakes during September 2001 to April 2002 and were analysed for salinity, nitrite, phosphate, ammonia, silicate and suspended material in water. The results of the study showed considerable variations in water quality depending upon the location along the coast in the vicinity of LBOD and RDs. The salinity ranged between 4.39–65.25 ppt in Tidal Link Drain samples whereas 2.4–38.05 ppt in samples collected from lakes. The values of suspended material at various RDs of Tidal Link Drain ranged between 56.6–2134 ppm and at the lakes between 68–297 ppm. The data of continuous monitoring at RD–93 showed the range of PO4 (8.6–25.2 μg/l), SiO3 (554.96–1462 μg/l), NO2 (0.557.2–25.2 μg/l) and NH3 (9.38–23.62 μg/l). The concentration of nutrients in water samples collected from different RDs was found in the range of PO4 (10.85 to 11.47 μg/l), SiO3 (1624 to 2635.08 μg/l), NO2 (20.38 to 44.8 μg/l) and NH3 (24.08 to 26.6 μg/l). Sindh coastal areas which situated at the north-western boundary the Arabian Sea are highly vulnerable to flood damages due to flash floods during SW monsoon or impact of sea level rise and storm surges coupled with cyclones passing through Arabian Sea along Pakistan coast. It is hoped that the obtained data in this study would act as a database for future investigations and monitoring of LBOD and Tidal Link Drain coastal waters.

Keywords: Tidal Link Drain, Salinity, Nutrients, Nitrite salts, Coastal areas.

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Authors: Dawit Burusie Abdi, Mamidala Jagadesh Kumar

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In this paper, using 2D TCAD simulations, the application of a dual material gate (DMG) for suppressing ambipolar conduction in a tunnel field effect transistor (TFET) is demonstrated. Using the proposed DMG concept, the ambipolar conduction can be effectively suppressed even if the drain doping is as high as that of the source doping. Achieving this symmetrical doping, without the ambipolar conduction in TFETs, gives the advantage of realizing both n-type and p-type devices with the same doping sequences. Furthermore, the output characteristics of the DMG TFET exhibit a good saturation when compared to that of the gate-drain underlap approach. This improved behavior of the DMG TFET makes it a good candidate for inverter based logic circuits.

Keywords: Dual material gate, suppressing ambipolar current, symmetrically doped TFET, tunnel FETs, PNPN TFET.

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Authors: Muhibul Haque Bhuyan, Quazi D. M. Khosru

Abstract:

Carriers scattering in the inversion channel of n- MOSFET dominates the drain current. This paper presents an effective electron mobility model for the pocket implanted nano scale n-MOSFET. The model is developed by using two linear pocket profiles at the source and drain edges. The channel is divided into three regions at source, drain and central part of the channel region. The total number of inversion layer charges is found for these three regions by numerical integration from source to drain ends and the number of depletion layer charges is found by using the effective doping concentration including pocket doping effects. These two charges are then used to find the effective normal electric field, which is used to find the effective mobility model incorporating the three scattering mechanisms, such as, Coulomb, phonon and surface roughness scatterings as well as the ballistic phenomena for the pocket implanted nano-scale n-MOSFET. The simulation results show that the derived mobility model produces the same results as found in the literatures.

Keywords: Linear Pocket Profile, Pocket Implanted n-MOSFET, Effective Electric Field and Effective Mobility Model.

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Authors: Cheng-Hsien Chang, Jyi-Tsong Lin, Po-Hsieh Lin, Hung-Pei Hsu, Chan-Hsiang Chang, Ming-Tsung Shih, Shih-Chuan Tseng, Min-Yan Lin

Abstract:

In this paper, we have proposed a novel FinFET with extended body under the poly gate, which is called EB-FinFET, and its characteristic is demonstrated by using three-dimensional (3-D) numerical simulation. We have analyzed and compared it with conventional FinFET. The extended body height dependence on the drain induced barrier lowering (DIBL) and subthreshold swing (S.S) have been also investigated. According to the 3-D numerical simulation, the proposed structure has a firm structure, an acceptable short channel effect (SCE), a reduced series resistance, an increased on state drain current (I on) and a large normalized I DS. Furthermore, the structure can also improve corner effect and reduce self-heating effect due to the extended body. Our results show that the EBFinFET is excellent for nanoscale device.

Keywords: SOI, FinFET, tri-gate, self-heating effect.

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Authors: Hung-Pei Hsu, Jyi-Tsong Lin, Po-Hsieh Lin, Cheng-Hsien Chang, Ming-Tsung Shih, Chan-Hsiang Chang, Shih-Chuan Tseng, Min-Yan Lin, Shih-Wen Hsu

Abstract:

In this paper, we propose a novel metal oxide semiconductor field effect transistor with L-shaped channel structure (LMOS), and several type of L-shaped structures are also designed, studied and compared with the conventional MOSFET device for the same average gate length (Lavg). The proposed device electrical characteristics are analyzed and evaluated by three dimension (3-D) ISE-TCAD simulator. It can be confirmed that the LMOS devices have higher on-state drain current and both lower drain-induced barrier lowering (DIBL) and subthreshold swing (S.S.) than its conventional counterpart has. In addition, the transconductance and voltage gain properties of the LMOS are also improved.

Keywords: Average gate length (Lavg), drain-induced barrier lowering (DIBL), L-shaped channel MOSFET (LMOS), subthreshold swing (S.S.).

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Authors: C. Papapicco

Abstract:

Motherhood is an existential human relationship that lasts for the whole life and is always interwoven with subjectivity and culture. As a result of the brain drain, the motherhood becomes motherhood at distance. Starting from the hypothesis that re-signification of the mother at distance practices is culturally relevant; the research aims to understand the experience of mother at a distance in order to extrapolate the strategies of management of the empty nest. Specifically, the research aims to evaluate the experience of a brain drain’s mother, who created a blog that intends to take care of other parents at a distance. Actually, the blog is the only artifact symbol of the Italian culture of motherhood at distance. In the research, a Netnographic Analysis of the blog mammedicervelliinfuga.com is offered with the aim of understanding if the online world becomes an opportunity to manage the role of mother at a distance. A narrative interview with the blog creator was conducted and then the texts were analyzed by means of a Diatextual Analysis approach. It emerged that the migration projects of talented children take on different meanings and representations for parents. Thus, it is shown that the blog becomes a new form of understanding and practicing motherhood at a distance.

Keywords: Brain drain, diatextual analysis, distance motherhood blog, online and offline narrations.

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Authors: Priyanka Malik A, Rishu Chaujar B, Mridula Gupta C, R.S. Gupta D

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In this paper, for the first time, a two-dimensional (2D) analytical drain current model for sub-100 nm multi-layered gate material engineered trapezoidal recessed channel (MLGMETRC) MOSFET: a novel design is presented and investigated using ATLAS and DEVEDIT device simulators, to mitigate the large gate leakages and increased standby power consumption that arise due to continued scaling of SiO2-based gate dielectrics. The twodimensional (2D) analytical model based on solution of Poisson-s equation in cylindrical coordinates, utilizing the cylindrical approximation, has been developed which evaluate the surface potential, electric field, drain current, switching metric: ION/IOFF ratio and transconductance for the proposed design. A good agreement between the model predictions and device simulation results is obtained, verifying the accuracy of the proposed analytical model.

Keywords: ATLAS, DEVEDIT, NJD, MLGME- TRCMOSFET.

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Authors: Ashwani K. Rana, Narottam Chand, Vinod Kapoor

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In this paper, gate leakage current has been mitigated by the use of novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure for the first time. A compact analytical model has been developed to study the gate leakage behaviour of proposed MOSFET structure. The result obtained has found good agreement with the Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. It is found that optimal Source/Drain-to-Gate Non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and DIBL characteristic. It is concluded that this structure solves the problem of high leakage current without introducing the extra series resistance.

Keywords: Gate tunneling current, analytical model, spacer dielectrics, DIBL, subthreshold slope.

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Authors: Fatemeh Karimi, Morteza Fathipour, Hamdam Ghanatian, Vala Fathipour

Abstract:

In this paper we investigate the electrical characteristics of a new structure of gate all around strained silicon nanowire field effect transistors (FETs) with dual dielectrics by changing the radius (RSiGe) of silicon-germanium (SiGe) wire and gate dielectric. Indeed the effect of high-κ dielectric on Field Induced Barrier Lowering (FIBL) has been studied. Due to the higher electron mobility in tensile strained silicon, the n-type FETs with strained silicon channel have better drain current compare with the pure Si one. In this structure gate dielectric divided in two parts, we have used high-κ dielectric near the source and low-κ dielectric near the drain to reduce the short channel effects. By this structure short channel effects such as FIBL will be reduced indeed by increasing the RSiGe, ID-VD characteristics will be improved. The leakage current and transfer characteristics, the threshold-voltage (Vt), the drain induced barrier height lowering (DIBL), are estimated with respect to, gate bias (VG), RSiGe and different gate dielectrics. For short channel effects, such as DIBL, gate all around strained silicon nanowire FET have similar characteristics with the pure Si one while dual dielectrics can improve short channel effects in this structure.

Keywords: SNWT (silicon nanowire transistor), Tensile Strain, high-κ dielectric, Field Induced Barrier Lowering (FIBL), cylindricalnano wire (CW), drain induced barrier lowering (DIBL).

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Authors: M. Khaouani, A. Guen-Bouazza, B. Bouazza, Z. Kourdi

Abstract:

The integrity and issues related to electrostatic performance associated with scaling Si MOSFET bulk sub 10nm channel length promotes research in new device architectures such as SOI, double gate and GAA MOSFET. In this paper, we present some novel characteristic of horizontal rectangular gate\gate all around MOSFETs with dual metal of gate we obtained using SILVACO TCAD tools. We will also exhibit some simulation results we obtained relating to the influence of some parameters variation on our structure, that having a direct impact on their threshold voltage and drain current. In addition, our TFET showed reasonable I_ON/I_OFF ratio of (10⁴) and low drain induced barrier lowering (DIBL) of 39 mV/V.

Keywords: GAA, SILVACO, QUANTUM, MOSFETs.

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Authors: Anwar Jarndal

Abstract:

In this paper, a genetic-neural-network (GNN) based large-signal model for GaN HEMTs is presented along with its parameters extraction procedure. The model is easy to construct and implement in CAD software and requires only DC and S-parameter measurements. An improved decomposition technique is used to model self-heating effect. Two GNN models are constructed to simulate isothermal drain current and power dissipation, respectively. The two model are then composed to simulate the drain current. The modeling procedure was applied to a packaged GaN-on-Si HEMT and the developed model is validated by comparing its large-signal simulation with measured data. A very good agreement between the simulation and measurement is obtained.

Keywords: GaN HEMT, computer-aided design & modeling, neural networks, genetic optimization.

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Authors: Pujarini Ghosh A, Rishu Chaujar B, Subhasis Haldar C, R.S Gupta D, Mridula Gupta E

Abstract:

In this paper, an analytical modeling is presentated to describe the channel noise in GME SGT/CGT MOSFET, based on explicit functions of MOSFETs geometry and biasing conditions for all channel length down to deep submicron and is verified with the experimental data. Results shows the impact of various parameters such as gate bias, drain bias, channel length ,device diameter and gate material work function difference on drain current noise spectral density of the device reflecting its applicability for circuit design applications.

Keywords: Cylindrical/Surrounded gate (SGT/CGT) MOSFET, Gate Material Engineering (GME), Spectral Noise and short channeleffect (SCE).

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Authors: Muhibul Haque Bhuyan, Quazi Deen Mohd Khosru

Abstract:

This paper presents a threshold voltage model of pocket implanted sub-100 nm n-MOSFETs incorporating the drain and substrate bias effects using two linear pocket profiles. Two linear equations are used to simulate the pocket profiles along the channel at the surface from the source and drain edges towards the center of the n-MOSFET. Then the effective doping concentration is derived and is used in the threshold voltage equation that is obtained by solving the Poisson-s equation in the depletion region at the surface. Simulated threshold voltages for various gate lengths fit well with the experimental data already published in the literature. The simulated result is compared with the two other pocket profiles used to derive the threshold voltage models of n-MOSFETs. The comparison shows that the linear model has a simple compact form that can be utilized to study and characterize the pocket implanted advanced ULSI devices.

Keywords: Linear pocket profile, pocket implantation, nMOSFET, threshold voltage, short channel effect (SCE), reverse short channeleffect (RSCE).

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Authors: Q. Zafar, R. Akram, Kh.S. Karimov, T.A. Khan, M. Farooq, M.M. Tahir

Abstract:

In this study we present the effect of elevated temperatures from 300K to 400K on the electrical properties of copper Phthalocyanine (CuPc) based organic field effect transistors (OFET). Thin films of organic semiconductor CuPc (40nm) and semitransparent Al (20nm) were deposited in sequence, by vacuum evaporation on a glass substrate with previously deposited Ag source and drain electrodes with a gap of 40 μm. Under resistive mode of operation, where gate was suspended it was observed that drain current of this organic field effect transistor (OFET) show an increase with temperature. While in grounded gate condition metal (aluminum) – semiconductor (Copper Phthalocyanine) Schottky junction dominated the output characteristics and device showed switching effect from low to high conduction states like Zener diode at higher bias voltages. This threshold voltage for switching effect has been found to be inversely proportional to temperature and shows an abrupt decrease after knee temperature of 360K. Change in dynamic resistance (Rd = dV/dI) with respect to temperature was observed to be -1%/K.

Keywords: Copper Phthalocyanine, Metal-Semiconductor Schottky Junction, Organic Field Effect Transistor, Switching effect, Temperature Sensor

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Authors: Muhibul Haque Bhuyan

Abstract:

This paper reports on the impact study with the variation of the gate insulation material and thickness on different models of pocket implanted sub-100 nm n-MOS device. The gate materials used here are silicon dioxide (SiO₂), aluminum silicate (Al₂SiO₅), silicon nitride (Si₃N₄), alumina (Al₂O₃), hafnium silicate (HfSiO₄), tantalum pentoxide (Ta₂O₅), hafnium dioxide (HfO₂), zirconium dioxide (ZrO₂), and lanthanum oxide (La₂O₃) upon a p-type silicon substrate material. The gate insulation thickness was varied from 2.0 nm to 3.5 nm for a 50 nm channel length pocket implanted n-MOSFET. There are several models available for this device. We have studied and simulated threshold voltage model incorporating drain and substrate bias effects, surface potential, inversion layer charge, pinch-off voltage, effective electric field, inversion layer mobility, and subthreshold drain current models based on two linear symmetric pocket doping profiles. We have changed the values of the two parameters, viz. gate insulation material and thickness gradually fixing the other parameter at their typical values. Then we compared and analyzed the simulation results. This study would be helpful for the nano-scaled MOS device designers for various applications to predict the device behavior.

Keywords: Linear symmetric pocket profile, pocket implanted n-MOS Device, model, impact of gate material, insulator thickness.

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Authors: Ashwani K. Rana, Narottam Chand, Vinod Kapoor

Abstract:

Aggressive scaling of MOS devices requires use of ultra-thin gate oxides to maintain a reasonable short channel effect and to take the advantage of higher density, high speed, lower cost etc. Such thin oxides give rise to high electric fields, resulting in considerable gate tunneling current through gate oxide in nano regime. Consequently, accurate analysis of gate tunneling current is very important especially in context of low power application. In this paper, a simple and efficient analytical model has been developed for channel and source/drain overlap region gate tunneling current through ultra thin gate oxide n-channel MOSFET with inevitable deep submicron effect (DSME).The results obtained have been verified with simulated and reported experimental results for the purpose of validation. It is shown that the calculated tunnel current is well fitted to the measured one over the entire oxide thickness range. The proposed model is suitable enough to be used in circuit simulator due to its simplicity. It is observed that neglecting deep sub-micron effect may lead to large error in the calculated gate tunneling current. It is found that temperature has almost negligible effect on gate tunneling current. It is also reported that gate tunneling current reduces with the increase of gate oxide thickness. The impact of source/drain overlap length is also assessed on gate tunneling current.

Keywords: Gate tunneling current, analytical model, gate dielectrics, non uniform poly gate doping, MOSFET, fringing field effect and image charges.

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Authors: Mohd Zulhilmi Suhaimi, Mohd Salehuddin Mohd Zahari

Abstract:

Common acceptable cuisine usually discussed in the multicultural/ethnic nation as it represents the process of sharing it among the ethnic groups. The common acceptable cuisine is also considered as a precursor in the process of constructing the national food identity within ethnic groups in the multicultural countries. The adaptation of certain ethnic cuisines through its types of food, methods of cooking, ingredients and eating decorum by ethnic groups is believed creating or enhancing the process of formation on common acceptable cuisines in a multicultural country. Malaysia as the multicultural country without doubt is continuing to experience cross-culturing processes among the ethnic groups including cuisine. This study empirically investigates the adaptation level of Malay, Chinese and Indian chefs on each other ethnic cuisine attributes toward the formation on common acceptable cuisines and national food identity.

Keywords: Common acceptable cuisine, adaptation, ethnic, food, identity.

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Authors: A. M. R. Mosalman Yazdi, B. A. R. Mosalman Yazdi

Abstract:

In industry, on of the most important subjects is die and it's characteristics in which for cutting and forming different mechanical pieces, various punch and matrix metal die are used. whereas the common parts which form the main frame die are not often proportion with pieces and dies therefore using a part as socalled common part for frames in specified dimension ranges can decrease the time of designing, occupied space of warehouse and manufacturing costs. Parts in dies with getting uniform in their shape and dimension make common parts of dies. Common parts of punch and matrix metal die are as bolster, guide bush, guide pillar and shank. In this paper the common parts and effective parameters in selecting each of them as the primary information are studied, afterward for selection and design of mechanical parts an introduction and investigation based on the Mech. Desk. software is done hence with developing this software can standardize the metal common parts of punch and matrix. These studies will be so useful for designer in their designing and also using it has with very much advantage for manufactures of products in decreasing occupied spaces by dies.

Keywords: Die, Matrix, Punch, Standardize.

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Authors: Jae Young Park, Seung Wook Lee, Jong Tae Kim

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OpenMP is an API for parallel programming model of shared memory multiprocessors. Novice OpenMP programmers often produce the code that compiler cannot find human errors. It was investigated how compiler coped with the common mistakes that can occur in OpenMP code. The latest version(4.4.3) of GCC is used for this research. It was found that GCC compiled the codes without any errors or warnings. In this paper the programming aid tool is presented for OpenMP programs. It can check 12 common mistakes that novice programmer can commit during the programming of OpenMP. It was demonstrated that the programming aid tool can detect the various common mistakes that GCC failed to detect.

Keywords: Parallel programming, OpenMP, programming aid.

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Authors: Alireza Tavakolinia

Abstract:

In order to understand the role of the injured party's fault in dividing liability, we studied its historical background. In common law, the traditional contributory negligence rule was a complete defense. Then the legislature and judicial procedure modified that rule to one of apportionment. In Islamic law, too, the Action rule was at first used when the injured party was the sole cause, but jurists expanded the scope of this rule, so this rule was used in cases where both the injured party's fault and that of the other party are involved. There are some popular approaches for apportionment of damages. Some common law countries like Britain had chosen ‘the causal potency approach’ and ‘fixed apportionment’. Islamic countries like Iran have chosen both ‘the relative blameworthiness’ and ‘equal apportionment’ approaches. The article concludes that both common law and Islamic law believe in the division of responsibility between a wrongdoer claimant and the defendant. In contrast, in the apportionment of responsibility, Islamic law mostly believes in equal apportionment that is way easier and saves time and money, but common law legal systems have chosen the causal potency approach which is more complicated than the rival approach but is fairer.

Keywords: Contributory negligence, common law, Islamic Law, Tort Law.

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Authors: M. A. Malakoutian, V. Fathipour, M. Fathipour, A. Mojab, M. M. Allame, M. Moradinasab

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In this paper, we have examined the effect of process parameter variation on the electrical characteristics of an LDMOS device. The rate of change in the electrical parameters such as cut off frequency, breakdown voltage and drain saturation current as a function of the process parameters is investigated

Keywords: LDMOS, Process Parameters, characteristics, parameter variation.

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Authors: N. Parimala, P. Pahwa

Abstract:

OLAP uses multidimensional structures, to provide access to data for analysis. Traditionally, OLAP operations are more focused on retrieving data from a single data mart. An exception is the drill across operator. This, however, is restricted to retrieving facts on common dimensions of the multiple data marts. Our concern is to define further operations while retrieving data from multiple data marts. Towards this, we have defined six operations which coalesce data marts. While doing so we consider the common as well as the non-common dimensions of the data marts.

Keywords: Data warehouse, Dimension, OLAP, Star Schema.

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Authors: Markéta Slováková

Abstract:

The largest share of policy and money within the European Union goes to agriculture. The Union’s Common Agricultural Policy has undergone several transformations in the last five decades, with the main change taking place in the 1990s. This change influenced agriculture in the Czech Republic, inasmuch as the fledgling republic was preparing to join the European Union and adopt its policies. In the 1990s, Czech agriculture passed from a centrally planned economy to a market economy and subsequently adopted the terms of the Common Agricultural Policy. The Czech Republic is also characterized by a significant diversification of landscape sphere. Agricultural entrepreneurs in the Czech Republic are still not accustomed to the possibility of grants from the European Union. They focus rather on national or regional subsidies. Only half of all agricultural entrepreneurs in the Czech Republic use European subsidies. This article focuses on the introduction of the Common Agricultural Policy to the Czech Republic and its subsequent influence on Czech agriculture. It is demonstrated through the implementation rate of the CAP in the EU Member States and a closer focus on Czech integration.

Keywords: Common Agricultural Policy, Agriculture, European Union, Transformation.

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Authors: Alemayehu Geremew Negash

Abstract:

In this paper, we prove some common fixed point theorems for co-cyclic weak contractions in compact metric spaces.

Keywords: Cyclic weak contraction, Co-cyclic weak contraction, Co-cyclic representation, Common fixed point.

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