Search results for: SNWT (silicon nanowire transistor)

Authors: C. M. M. Paschoal, M. L. Sobrinho, D. do N. Souza, J. Antônio Filho, L. A. P. Santos

Abstract:

Computed tomography (CT) dosimetry normally uses an ionization chamber 100 mm long to estimate the computed tomography dose index (CTDI), however some reports have already indicated that small devices could replace the long ion chamber to improve quality assurance procedures in CT dosimetry. This paper presents a novel dosimetry system based in a commercial phototransistor evaluated for CT dosimetry. Three detector configurations were developed for this system: with a single, two and four devices. Dose profile measurements were obtained with them and their angular response were evaluated. The results showed that the novel dosimetry system with the phototransistor could be an alternative for CT dosimetry. It allows to obtain the CT dose profile in details and also to estimate the CTDI in longer length than the 100 mm pencil chamber. The angular response showed that the one device detector configuration is the most adequate among the three configurations analyzed in this study.

Keywords: Computed tomography, dosimetry, photo-transistor

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Authors: Hai-Qing Xie, Yun Zeng, Yong-Hong Yan, Jian-Ping Zeng, Tai-Hong Wang

Abstract:

Photo-BJMOSFET (Bipolar Junction Metal-Oxide- Semiconductor Field Effect Transistor) fabricated on SOI film was proposed. ITO film is adopted in the device as gate electrode to reduce light absorption. Depletion region but not inversion region is formed in film by applying gate voltage (but low reverse voltage) to achieve high photo-to-dark-current ratio. Comparisons of photoelectriccharacteristics executed among VGK=0V, 0.3V, 0.6V, 0.9V and 1.0V (reverse voltage VAK is equal to 1.0V for total area of 10×10μm2). The results indicate that the greatest improvement in photo-to-dark-current ratio is achieved up to 2.38 at VGK=0.6V. In addition, photo-BJMOSFET is compatible with CMOS integration due to big input resistance

Keywords: Photo-BJMOSFET, Responsivity, Sensitivity, Spectral response.

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Authors: Ivelina N. Cholakova, Tihomir B. Takov, Radostin Ts. Tsankov, Nicolas Simonne, Slavka S. Tzanova

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Adjacent Hall microsensors, comprising a silicon substrate and four contacts, providing simultaneously two supply inputs and two differential outputs, are characterized. The voltage related sensitivity is in the order of 0.11T-1, and a cancellation method for offset compensation is used, achieving residual offset in the micro scale which is also compared to a single Hall plate.

Keywords: Adjacent Hall sensors, offset compensation, voltage related sensitivity, 0.18μm CMOS technology.

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Authors: P.K. Sharma, B. Bhargava, S. Akashe

Abstract:

Power dissipation due to leakage current in the digital circuits is a biggest factor which is considered specially while designing nanoscale circuits. This paper is exploring the ideas of reducing leakage current in static CMOS circuits by stacking the transistors in increasing numbers. Clearly it means that the stacking of OFF transistors in large numbers result a significant reduction in power dissipation. Increase in source voltage of NMOS transistor minimizes the leakage current. Thus stacking technique makes circuit with minimum power dissipation losses due to leakage current. Also some of digital circuits such as full adder, D flip flop and 6T SRAM have been simulated in this paper, with the application of reduction technique on ‘cadence virtuoso tool’ using specter at 45nm technology with supply voltage 0.7V.

Keywords: Stack, 6T SRAM cell, low power, threshold voltage

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Authors: N. Massoum, A. Guen. Bouazza, B. Bouazza, A. El Ouchdi

Abstract:

The progress of industry integrated circuits in recent years has been pushed by continuous miniaturization of transistors. With the reduction of dimensions of components at 0.1 micron and below, new physical effects come into play as the standard simulators of two dimensions (2D) do not consider. In fact the third dimension comes into play because the transverse and longitudinal dimensions of the components are of the same order of magnitude. To describe the operation of such components with greater fidelity, we must refine simulation tools and adapted to take into account these phenomena. After an analytical study of the static characteristics of the component, according to the different operating modes, a numerical simulation is performed of field-effect transistor with submicron gate MESFET GaInP. The influence of the dimensions of the gate length is studied. The results are used to determine the optimal geometric and physical parameters of the component for their specific applications and uses.

Keywords: Monte Carlo simulation, transient electron transport, MESFET device.

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Authors: Ankit Mitra

Abstract:

An adder is one of the most integral component of a digital system like a digital signal processor or a microprocessor. Being an extremely computationally intensive part of a system, the optimization for speed and power consumption of the adder is of prime importance. In this paper we have designed a 1 bit full adder cell based on dynamic TSPC logic to achieve high speed operation. A high threshold voltage sleep transistor is used to reduce the static power dissipation in standby mode. The circuit is designed and simulated in TSPICE using TSMC 180nm CMOS process. Average power consumption, delay and power-delay product is measured which showed considerable improvement in performance over the existing full adder designs.

Keywords: CMOS, TSPC, MTCMOS, ALU, Clock gating, power gating, pipelining.

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Authors: Mohd. Hasan, Ajmal Kafeel, S. D. Pable

Abstract:

Ultra-low-power (ULP) circuits have received widespread attention due to the rapid growth of biomedical applications and Battery-less Electronics. Subthreshold region of transistor operation is used in ULP circuits. Major research challenge in the subthreshold operating region is to extract the ULP benefits with minimal degradation in speed and robustness. Process, Voltage and Temperature (PVT) variations significantly affect the performance of subthreshold circuits. Designed performance parameters of ULP circuits may vary largely due to temperature variations. Hence, this paper investigates the effect of temperature variation on device and circuit performance parameters at different biasing voltages in the subthreshold region. Simulation results clearly demonstrate that in deep subthreshold and near threshold voltage regions, performance parameters are significantly affected whereas in moderate subthreshold region, subthreshold circuits are more immune to temperature variations. This establishes that moderate subthreshold region is ideal for temperature immune circuits.

Keywords: Subthreshold, temperature variations, ultralow power.

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Authors: Kensuke Akiyama, Satoru Kaneko, Takeshi Ozawa, Kazuya Yokomizo, Masaru Itakura

Abstract:

The photoluminescence (PL) at 1.55 μm from semiconducting β-FeSi2 has attracted a noticeable interest for silicon-based optoelectronic applications. Moreover, its high optical absorption coefficient (higher than 105 cm-1 above 1.0 eV) allows this semiconducting material to be used as photovoltanics devices. A clear PL spectrum for β-FeSi2 was observed by Cu or Au coating on Si(001). High-crystal-quality β-FeSi2 with a low-level nonradiative center was formed on a Cu- or Au- reated Si layer. This method of deposition can be applied to other materials requiring high crystal quality.

Keywords: iron silicide, semiconductor, epitaxial, photoluminescence.

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Authors: Hema Sandhya Jagarlamudi, Mousumi Saha, Pavan Kumar Jagarlamudi

Abstract:

The use of Quantum dots is a promising emerging Technology for implementing digital system at the nano level. It is effecient for attractive features such as faster speed , smaller size and low power consumption than transistor technology. In this paper, various Combinational and sequential logical structures - HALF ADDER, SR Latch and Flip-Flop, D Flip-Flop preceding NAND, NOR, XOR,XNOR are discussed based on QCA design, with comparatively less number of cells and area. By applying these layouts, the hardware requirements for a QCA design can be reduced. These structures are designed and simulated using QCA Designer Tool. By taking full advantage of the unique features of this technology, we are able to create complete circuits on a single layer of QCA. Such Devices are expected to function with ultra low power Consumption and very high speeds.

Keywords: QCA, QCA Designer, Clock, Majority Gate

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Authors: Hung-Pei Hsu, Jyi-Tsong Lin, Po-Hsieh Lin, Cheng-Hsien Chang, Ming-Tsung Shih, Chan-Hsiang Chang, Shih-Chuan Tseng, Min-Yan Lin, Shih-Wen Hsu

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In this paper, we propose a novel metal oxide semiconductor field effect transistor with L-shaped channel structure (LMOS), and several type of L-shaped structures are also designed, studied and compared with the conventional MOSFET device for the same average gate length (Lavg). The proposed device electrical characteristics are analyzed and evaluated by three dimension (3-D) ISE-TCAD simulator. It can be confirmed that the LMOS devices have higher on-state drain current and both lower drain-induced barrier lowering (DIBL) and subthreshold swing (S.S.) than its conventional counterpart has. In addition, the transconductance and voltage gain properties of the LMOS are also improved.

Keywords: Average gate length (Lavg), drain-induced barrier lowering (DIBL), L-shaped channel MOSFET (LMOS), subthreshold swing (S.S.).

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Authors: Antonis Constantinides, Christos Yiallouras, Christakis Damianou

Abstract:

The application of today's semiconductor transistors in high power UHF DVB-T linear amplifiers has evolved significantly by utilizing LDMOS technology. This fact provides engineers with the option to design a single transistor signal amplifier which enables output power and linearity that was unobtainable previously using bipolar junction transistors or later type first generation MOSFETS. The quiescent current stability in terms of thermal variations of the LDMOS guarantees a robust operation in any topology of DVB-T signal amplifiers. Otherwise, progressively uncontrolled heat dissipation enhancement on the LDMOS case can degrade the amplifier’s crucial parameters in regards to the gain, linearity and RF stability, resulting in dysfunctional operation or a total destruction of the unit. This paper presents one more sophisticated approach from the traditional biasing circuits used so far in LDMOS DVB-T amplifiers. It utilizes a microprocessor control technology, providing stability in topologies where IDQ must be perfectly accurate.

Keywords: Amplifier, DVB-T, LDMOS, MOSFETS.

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Authors: Robert Setekera, Luuk Tiemeijer, Ramses van der Toorn

Abstract:

In this paper an extensive verification of the extraction method (published earlier) that consistently accounts for self-heating and Early effect to accurately extract both base and thermal resistance of bipolar junction transistors is presented. The method verification is demonstrated on advanced RF SiGe HBTs were the extracted results for the thermal resistance are compared with those from another published method that ignores the effect of Early effect on internal base-emitter voltage and the extracted results of the base resistance are compared with those determined from noise measurements. A self-consistency of our method in the extracted base resistance and thermal resistance using compact model simulation results is also carried out in order to study the level of accuracy of the method.

Keywords: Avalanche, Base resistance, Bipolar transistor, Compact modeling, Early voltage, Thermal resistance, Self-heating, parameter extraction.

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Authors: R .H. Talwekar, S. S Limaye

Abstract:

The designing of charge pump with high gain Op- Amp is a challenging task for getting faithful response .Design of high performance phase locked loop require ,a design of high performance charge pump .We have designed a operational amplifier for reducing the error caused by high speed glitch in a transistor and mismatch currents . A separate Op-Amp has designed in 180 nm CMOS technology by CADENCE VIRTUOSO tool. This paper describes the design of high performance charge pump for GHz CMOS PLL targeting orthogonal frequency division multiplexing (OFDM) application. A high speed low power consumption Op-Amp with more than 500 MHz bandwidth has designed for increasing the speed of charge pump in Phase locked loop.

Keywords: Charge pump (CP) Orthogonal frequency divisionmultiplexing (OFDM), Phase locked loop (PLL), Phase frequencydetector (PFD), Voltage controlled oscillator (VCO),

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Authors: S. Srinivas, N. Ramesh Babu

Abstract:

This paper presents a model to predict the depth of penetration in polycrystalline ceramic material cut by abrasive waterjet. The proposed model considered the interaction of cylindrical jet with target material in upper region and neglected the role of threshold velocity in lower region. The results predicted with the proposed model are validated with the experimental results obtained with Silicon Carbide (SiC) blocks.

Keywords: Abrasive waterjet cutting, analytical modeling, ceramics, microcutting and intergranular cracking.

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Authors: Subal Kar, Madhuja Ghosh, Soumik Das, Antara Saha

Abstract:

A novel technique has been developed to generate ultra-stable millimeter-wave signal by optical heterodyning of the output from two slave laser (SL) sources injection-locked to the sidebands of a frequency modulated (FM) master laser (ML). Precise thermal tuning of the SL sources is required to lock the particular slave laser frequency to the desired FM sidebands of the ML. The output signals from the injection-locked SL when coherently heterodyned in a fast response photo detector like high electron mobility transistor (HEMT), extremely stable millimeter-wave signal having very narrow line width can be generated. The scheme may also be used to generate ultra-stable sub-millimeter-wave/terahertz signal.

Keywords: FM sideband injection locking, Master-Slave injection locking, Millimetre-wave signal generation and Optical heterodyning.

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Authors: Siti Kudnie Sahari, Jane Chai Hai Sing, Khairuddin Ab. Hamid

Abstract:

Shrunken patterning for integrated device manufacturing requires surface cleanliness and surface smoothness in wet chemical processing [1]. It is necessary to control all process parameters perfectly especially for the common cleaning technique RCA clean (SC-1 and SC-2) [2]. In this paper the characteristic and effect of surface preparation parameters are discussed. The properties of RCA wet chemical processing in silicon technology is based on processing time, temperature, concentration and megasonic power of SC-1 and QDR. An improvement of wafer surface preparation by the enhanced variables of the wet cleaning chemical process is proposed.

Keywords: RCA, SC-1, SC-2, QDR

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Authors: Ala'eddin A. Saif , Z. A. Z. Jamal, Z. Sauli, P. Poopalan

Abstract:

The ferroelectric behavior of barium strontium titanate (BST) in thin film form has been investigated in order to study the possibility of using BST for ferroelectric gate-field effect transistor (FeFET) for memory devices application. BST thin films have been fabricated as Al/BST/Pt/SiO2/Si-gate configuration. The variation of the dielectric constant (ε) and tan δ with frequency have been studied to ensure the dielectric quality of the material. The results show that at low frequencies, ε increases as the Ba content increases, whereas at high frequencies, it shows the opposite variation, which is attributed to the dipole dynamics. tan δ shows low values with a peak at the mid-frequency range. The ferroelectric behavior of the Al/BST/Pt/SiO2/Si has been investigated using C-V characteristics. The results show that the strength of the ferroelectric hysteresis loop increases as the Ba content increases; this is attributed to the grain size and dipole dynamics effect.

Keywords: BST thin film, Electrical properties, Ferroelectrichysteresis, Ferroelectric FET.

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Authors: Houda Bdiri Gabbouj, Néjib Hassen, Kamel Besbes

Abstract:

This paper presents a low-voltage low-power differential linear transconductor with near rail-to-rail input swing. Based on the current-mirror OTA topology, the proposed transconductor combines the Flipped Voltage Follower (FVF) technique to linearize the transconductor behavior that leads to class- AB linear operation and the virtual transistor technique to lower the effective threshold voltages of the transistors which offers an advantage in terms of low supply requirement. Design of the OTA has been discussed. It operates at supply voltages of about ±0.8V. Simulation results for 0.18μm TSMC CMOS technology show a good input range of 1Vpp with a high DC gain of 81.53dB and a total harmonic distortion of -40dB at 1MHz for an input of 1Vpp. The main aim of this paper is to present and compare new OTA design with high transconductance, which has a potential to be used in low voltage applications.

Keywords: Amplifier class AB, current mirror, flipped voltage follower, low voltage.

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Authors: M. Fadlallah, G. Ghibaudo, C. G. Theodorou

Abstract:

The dynamic variation in memory devices such as the Static Random Access Memory can give errors in read or write operations. In this paper, the effect of low-frequency and random telegraph noise on the dynamic variation of one SRAM cell is detailed. The effect on circuit noise, speed, and length of time of processing is examined, using the Supply Read Retention Voltage and the Read Static Noise Margin. New test run methods are also developed. The obtained results simulation shows the importance of noise caused by dynamic variation, and the impact of Random Telegraph noise on SRAM variability is examined by evaluating the statistical distributions of Random Telegraph noise amplitude in the pull-up, pull-down. The threshold voltage mismatch between neighboring cell transistors due to intrinsic fluctuations typically contributes to larger reductions in static noise margin. Also the contribution of each of the SRAM transistor to total dynamic variation has been identified.

Keywords: Low-frequency noise, Random Telegraph Noise, Dynamic Variation, SRRV.

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Authors: Vincent King Soon Wong, Hong Seng Ng, Florinna Sim

Abstract:

Negative Bias Temperature Instability (NBTI) is one of the critical degradation mechanisms in semiconductor device reliability that causes shift in the threshold voltage (Vth). However, thorough understanding of this reliability failure mechanism is still unachievable due to a recovery characteristic known as NBTI recovery. This paper will demonstrate the severity of NBTI recovery as well as one of the effective methods used to mitigate, which is the minimization of measurement system delays. Comparison was done in between two measurement systems that have significant differences in measurement delays to show how NBTI recovery causes result deviations and how fast measurement systems can mitigate NBTI recovery. Another method to minimize NBTI recovery without the influence of measurement system known as Fast Wafer Level Reliability (FWLR) NBTI was also done to be used as reference.

Keywords: Fast vs slow BTI, Fast wafer level reliability, Negative bias temperature instability, NBTI measurement system, metal-oxide-semiconductor field-effect transistor, MOSFET, NBTI recovery, reliability.

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Authors: Kittipong Tripetch, Nobuhiko Nakano

Abstract:

Two types of floating active resistors based on a complementary regulated cascode topology with cross-coupled regulated transistors are presented in this paper. The first topology is a high swing complementary regulated cascode active resistor. The second topology is a complementary common gate with a regulated cross coupled transistor. The small-signal input resistances of the floating resistors are derived. Three graphs of the input current versus the input voltage for different aspect ratios are designed and plotted using the Cadence Spectre 0.18-µm Rohm Semiconductor process. The total harmonic distortion graphs are plotted for three different aspect ratios with different input-voltage amplitudes and different input frequencies. From the simulation results, it is observed that a resistance of approximately 8.52 MΩ can be obtained from supply voltage at  ±0.9 V.

Keywords: Complementary common gate, complementary regulated cascode, current mirror, floating active resistors.

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Authors: A. Lakrim, D. Tahri

Abstract:

This paper sets out a behavioral macro-model of a Merged PiN and Schottky (MPS) diode based on silicon carbide (SiC). This model holds good for both static and dynamic electrothermal simulations for industrial applications. Its parameters have been worked out from datasheets curves by drawing on the optimization method: Simulated Annealing (SA) for the SiC MPS diodes made available in the industry. The model also adopts the Analog Behavioral Model (ABM) of PSPICE in which it has been implemented. The thermal behavior of the devices was also taken into consideration by making use of Foster’ canonical network as figured out from electro-thermal measurement provided by the manufacturer of the device.

Keywords: SiC MPS Diode, electro-thermal, SPICE Model.

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Authors: Montree Kumngern, Kobchai Dejhan

Abstract:

Versatile dual-mode class-AB CMOS four-quadrant analog multiplier circuit is presented. The dual translinear loops and current mirrors are the basic building blocks in realization scheme. This technique provides; wide dynamic range, wide-bandwidth response and low power consumption. The major advantages of this approach are; its has single ended inputs; since its input is dual translinear loop operate in class-AB mode which make this multiplier configuration interesting for low-power applications; current multiplying, voltage multiplying, or current and voltage multiplying can be obtainable with balanced input. The simulation results of versatile analog multiplier demonstrate a linearity error of 1.2 %, a -3dB bandwidth of about 19MHz, a maximum power consumption of 0.46mW, and temperature compensated. Operation of versatile analog multiplier was also confirmed through an experiment using CMOS transistor array.

Keywords: Class-AB, dual-mode CMOS analog multiplier, CMOS analog integrated circuit, CMOS translinear integrated circuit.

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Authors: M. S. Said, J. A. Ghani, Che Hassan C. H., N. N. Wan, M. A. Selamat, R. Othman

Abstract:

Metal matrix composites (MMCs) attract considerable attention as a result from its ability in providing a high strength, high modulus, high toughness, high impact properties, improving wear resistance and providing good corrosion resistance compared to unreinforced alloy. Aluminium Silicon (Al/Si) alloy MMC has been widely used in various industrial sectors such as in transportation, domestic equipment, aerospace, military, construction, etc. Aluminium silicon alloy is an MMC that had been reinforced with aluminium nitrate (AlN) particle and become a new generation material use in automotive and aerospace sector. The AlN is one of the advance material that have a bright prospect in future since it has features such as lightweight, high strength, high hardness and stiffness quality. However, the high degree of ceramic particle reinforcement and the irregular nature of the particles along the matrix material that contribute to its low density is the main problem which leads to difficulties in machining process. This paper examined the tool wear when milling AlSi/AlN Metal Matrix Composite using a TiB2 (Titanium diboride) coated carbide cutting tool. The volume of the AlN reinforced particle was 10% and milling process was carried out under dry cutting condition. The TiB2 coated carbide insert parameters used were at the cutting speed of (230, 300 and 370m/min, feed rate of 0.8, Depth of Cut (DoC) at 0.4m). The Sometech SV-35 video microscope system used to quantify of the tool wear. The result shown that tool life span increasing with the cutting speeds at (370m/min, feed rate of 0.8mm/tooth and DoC at 0.4mm) which constituted an optimum condition for longer tool life lasted until 123.2 mins. Meanwhile, at medium cutting speed which at 300m/m, feed rate of 0.8mm/tooth and depth of cut at 0.4mm we found that tool life span lasted until 119.86 mins while at low cutting speed it lasted in 119.66 mins. High cutting speed will give the best parameter in cutting AlSi/AlN MMCs material. The result will help manufacturers in machining process of AlSi/AlN MMCs materials.

Keywords: AlSi/AlN Metal Matrix Composite milling process, tool wear, TiB2 coated cemented carbide tool.

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Authors: Bo Bae Song, Byung Seok Lee, Hyun Young Kim, Chung Kwang Lee, Yong Seo Koo

Abstract:

This paper proposed a silicon controller rectifier (SCR) based ESD protection device to protect low voltage ESD for integrated circuit. The proposed ESD protection device has low trigger voltage and high holding voltage compared with conventional SCR-based ESD protection devices. The proposed ESD protection circuit is verified and compared by TCAD simulation. This paper verified effective low voltage ESD characteristics with low trigger voltage of 5.79V and high holding voltage of 3.5V through optimization depending on design variables (D1, D2, D3 and D4).

Keywords: ESD, SCR, Holding voltage, Latch-up.

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Authors: Rizwan Asghar, Dake Liu

Abstract:

The direct implementation of interleaver functions in WiMAX is not hardware efficient due to presence of complex functions. Also the conventional method i.e. using memories for storing the permutation tables is silicon consuming. This work presents a 2-D transformation for WiMAX channel interleaver functions which reduces the overall hardware complexity to compute the interleaver addresses on the fly. A fully reconfigurable architecture for address generation in WiMAX channel interleaver is presented, which consume 1.1 k-gates in total. It can be configured for any block size and any modulation scheme in WiMAX. The presented architecture can run at a frequency of 200 MHz, thus fully supporting high bandwidth requirements for WiMAX.

Keywords: Interleaver, deinterleaver, WiMAX, 802.16e.

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Authors: Nadezhda Nikolaeva, Tatyana Alexandrova, Alexandr Alexandrov

Abstract:

Processing of high-silicon bauxite on the base of the traditional clinkering method is related to high power consumption and capital investments, which makes production of alumina from those ores non-competitive in terms of basic economic showings. For these reasons, development of technological solutions enabling to process bauxites with various chemical and mineralogical structures efficiently with low level of thermal power consumption is important. Flow sheet of the studies on washability of ores from the Timanskoe and the Severo-Onezhskoe deposits is on the base of the flotation method.

Keywords: Low-quality bauxite, resource-saving technology, optimization, aluminum, conditioning of composition, separation characteristics.

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Authors: S. Y. Choi, Y. H. Na, J. H. Kim

Abstract:

In this work, thermoelastic damping effect on the hemi- spherical shells is investigated. The material is selected silicon, and heat conduction equation for thermal flow is solved to obtain the temperature profile in which bending approximation with inextensional assumption of the model. Using the temperature profile, eigen-value analysis is performed to get the natural frequencies of hemispherical shells. Effects of mode numbers, radii and radial thicknesses of the model on the natural frequencies are analyzed in detail. Furthermore, the quality factor (Q-factor) is defined, and discussed for the ring and hemispherical shell.

Keywords: Thermoelastic damping, hemispherical shell, quality factor

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Authors: Yong Seo Koo, Dong Su Kim, Byung Seok Lee, Won Suk Park, Bo Bea Song

Abstract:

This paper presents a SCR-based ESD protection devices for I/O clamp and power rail clamp, respectably. These devices have a low trigger voltage and high holding voltage characteristics than conventional SCR device. These devices are fabricated by using 0.35um BCD (Bipolar-CMOS-DMOS) processes. These devices were validated using a TLP system. From the experimental results, the device for I/O ESD clamp has a trigger voltage of 5.8V. Also, the device for power rail ESD clamp has a holding voltage of 7.7V.

Keywords: ESD (Electro-Static Discharge), ESD protection device, SCR (Silicon Controlled Rectifier), Latch-up

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Authors: Shanmuka Naga Raju

Abstract:

This paper  presents PV system without considering transformer connected to electric grid. This is considered more economic compared to present PV system. The problem that occurs when transformer is not considered appears with a leakage current near capacitor connected to ground. Bipolar Pulse Width Modulation (BPWM) technique along with filter L-C-L configuration in the circuit is modeled to shrink the leakage current in the circuit. The DC/AC inverter is modeled using H-bridge Insulated Gate Bipolar Transistor (IGBT) module which is controlled using proposed Bipolar PWM control technique. To extract maximum power, Maximum Power Point Technique (MPPT) controller is used in this model. Voltage and current regulators are used to determine the reference voltage for the inverter from active and reactive current where reactive current is set to zero. The PLL is modeled to synchronize the measurements. The model is designed with MATLAB Simulation blocks and compared with the methods available in literature survey to show its effectiveness.

Keywords: Photovoltaic, PV, pulse width modulation, PWM, perturb and observe, phase locked loop.

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