Commenced in January 2007
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Edition: International
Paper Count: 30172
2-D Realization of WiMAX Channel Interleaver for Efficient Hardware Implementation

Authors: Rizwan Asghar, Dake Liu

Abstract:

The direct implementation of interleaver functions in WiMAX is not hardware efficient due to presence of complex functions. Also the conventional method i.e. using memories for storing the permutation tables is silicon consuming. This work presents a 2-D transformation for WiMAX channel interleaver functions which reduces the overall hardware complexity to compute the interleaver addresses on the fly. A fully reconfigurable architecture for address generation in WiMAX channel interleaver is presented, which consume 1.1 k-gates in total. It can be configured for any block size and any modulation scheme in WiMAX. The presented architecture can run at a frequency of 200 MHz, thus fully supporting high bandwidth requirements for WiMAX.

Keywords: Interleaver, deinterleaver, WiMAX, 802.16e.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1333424

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References:


[1] IEEE 802.16e-2005: "IEEE Standard for local and metropolitan area networks, Part 16: Air Interface for Fixed Broadband Wireless Access Systems - Amendment 2: Medium Access Control Layers for Combined Fixed and Mobile Operations in Licensed Bands."
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