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Versatile Dual-Mode Class-AB Four-Quadrant Analog Multiplier

Authors: Montree Kumngern, Kobchai Dejhan


Versatile dual-mode class-AB CMOS four-quadrant analog multiplier circuit is presented. The dual translinear loops and current mirrors are the basic building blocks in realization scheme. This technique provides; wide dynamic range, wide-bandwidth response and low power consumption. The major advantages of this approach are; its has single ended inputs; since its input is dual translinear loop operate in class-AB mode which make this multiplier configuration interesting for low-power applications; current multiplying, voltage multiplying, or current and voltage multiplying can be obtainable with balanced input. The simulation results of versatile analog multiplier demonstrate a linearity error of 1.2 %, a -3dB bandwidth of about 19MHz, a maximum power consumption of 0.46mW, and temperature compensated. Operation of versatile analog multiplier was also confirmed through an experiment using CMOS transistor array.

Keywords: Class-AB, dual-mode CMOS analog multiplier, CMOS analog integrated circuit, CMOS translinear integrated circuit

Digital Object Identifier (DOI):

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[1] P. E. Allen and D. R. Golberg, CMOS Analog circuit design. Holt Rinehart and Winston, Inc. 1987.
[2] K. Bult and H. Wallinga, "A CMOS four-quadrant analog multiplier," IEEE J. Solid-State Circuit, vol. SC-21, pp. 430-435, June 1986.
[3] J. S. Pena-Finol and J. A. Connelly, "A MOS four-quadrant analog multiplier using the quarter-square technique," IEEE J. Solid-State Circuit, vol. SC-22, pp. 1064-1073, December 1987.
[4] H.-J. Song and C.-K. Kim, "An MOS four-quadrant analog multiplier using simple two-input squaring circuit with source follower," IEEE Journal of Solid-State Circuits, vol. 25, pp. 841-848, June 1990.
[5] S.-I. Liu and C.-C. Chang, "CMOS analog divider and four-quadrant multiplier using pool circuits," IEEE Journal Solid-State Circuits, vol. 30, pp. 1025-1029, September 1995.
[6] S.-I. Liu and C.-C. Chang, "CMOS four-quadrant multiplier using active attenuation," Int. J. Electronics, vol. 79, pp. 323-328, 1995.
[7] H. R. Mehrvarz, and C. Y. Kwok, "A novel multi-input floating-gate MOS four-quadrant analog multiplier," IEEE Journal of Solid-State Circuits, vol. 31, pp. 1123-1131, August 1997.
[8] J.-J. Chen, S.-I. Liu, and Y.-S Hwang, "Low-voltage single power supply four-quadrant multiplier using floating-gate MOSFETs," IEE Proc. -Circuits Devices Syst., vol. 145, pp. 40-43, February 1998.
[9] S. Vlassis and S. Siskos, "Analogue squarer and multiplier based on floating-gate MOS transistors," Electron. Letts., vol. 32, pp. 825-827, April 1998.
[10] B. J. Blalock and S. A. Jackson, "A 1.2-V CMOS four-quadrant analog multiplier," 1999 Southwest Symposium on mixed-signal design (SSMSD -99), pp. 1-4, 1999.
[11] D. Coue and G. Wilson, "A four-quadrant subthreshold mode multiplier for analog neural-network applications," IEEE Transactions on Neural Networks, vol. 7, pp. 1212-1219, September 1996.
[12] S.-I. Liu and C.-C. Chang, "CMOS subthreshold four-quadrant multiplier based on unbalanced source-coupled pairs," Int. J. Electronics, vol. 78, pp. 327-332, 1995.
[13] C.-C. Chang and S.-I. Liu, "Weak inversion four-quadrant multiplier and two-quadrant divider," Electron. Letts., vol. 34, pp. 2079-2080, October 1996.
[14] O. Oliaei and P. Loumeau, "Four-quadrant class AB CMOS current multiplier," Electron. Letts., vol. 32, pp. 2327-2329, December 1996.
[15] K. Wawryn, "AB class current mode multipliers for programmable neural networks," Electron. Letts., vol. 32, pp. 1902-1904, September 1996.
[16] I. Chaisayun and K. Dejhan, "A versatile CMOS analog multiplier," IEICE Trans. Fundamentals, vol. E86-A, pp. 1225-1231, May 2003.
[17] I. Chaisayun, and K. Dejhan, "A low-voltage, versatile CMOS fourquadrant analogue multiplier," Int. J. Electronics, vol. 90, pp. 635-644, October 2003.
[18] W. Surakampontorn and K. Kumwachara, "A dual translinear-based true RMS-to-DC converter," IEEE Trans. Instrumentation and Measurement, vol. 47, pp. 459-464, April 1998.
[19] A. Fabre, "New formulation to describe translinear mixed cells accurately," Proc. Inst. Elect. Eng., vol. 141, pt. G, pp. 167-173, 1994.
[20] E. Seevinck and R. J. Wiegerink, "Generalized translinear circuit principle," IEEE Journal of Solid-State Circuits, vol. 26, pp. 1098-1102, August 1991.
[21] Z. Wang, "2-MOSFET transistor with extremely low distortion for output reaching supply voltage," Electron. Letts., vol. 26, pp. 951-952, June 1990.