Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 1194

Search results for: threshold voltage

1194 C-V Characterization and Analysis of Temperature and Channel Thickness Effects on Threshold Voltage of Ultra-thin SOI MOSFET by Self-Consistent Model

Authors: Shuvro Chowdhury, Esmat Farzana, Rizvi Ahmed, A. T. M. Golam Sarwar, M. Ziaur Rahman Khan

Abstract:

The threshold voltage and capacitance voltage characteristics of ultra-thin Silicon-on-Insulator MOSFET are greatly influenced by the thickness and doping concentration of the silicon film. In this work, the capacitance voltage characteristics and threshold voltage of the device have been analyzed with quantum mechanical effects using the Self-Consistent model. Reduction of channel thickness and adding doping impurities cause an increase in the threshold voltage. Moreover, the temperature effects cause a significant amount of threshold voltage shift. The temperature dependence of threshold voltage has also been observed with Self- Consistent approach which are well supported from experimental performance of practical devices.

Keywords: C-V characteristics, Self-Consistent Analysis, Siliconon-Insulator, Ultra-thin film.

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1193 Linear Pocket Profile based Threshold Voltage Model for sub-100 nm n-MOSFET

Authors: Muhibul Haque Bhuyan, Quazi Deen Mohd Khosru

Abstract:

This paper presents a threshold voltage model of pocket implanted sub-100 nm n-MOSFETs incorporating the drain and substrate bias effects using two linear pocket profiles. Two linear equations are used to simulate the pocket profiles along the channel at the surface from the source and drain edges towards the center of the n-MOSFET. Then the effective doping concentration is derived and is used in the threshold voltage equation that is obtained by solving the Poisson-s equation in the depletion region at the surface. Simulated threshold voltages for various gate lengths fit well with the experimental data already published in the literature. The simulated result is compared with the two other pocket profiles used to derive the threshold voltage models of n-MOSFETs. The comparison shows that the linear model has a simple compact form that can be utilized to study and characterize the pocket implanted advanced ULSI devices.

Keywords: Linear pocket profile, pocket implantation, nMOSFET, threshold voltage, short channel effect (SCE), reverse short channeleffect (RSCE).

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1192 Investigation of Threshold Voltage Shift in Gamma Irradiated N-Channel and P-Channel MOS Transistors of CD4007

Authors: S. Boorboor, S. A. H. Feghhi, H. Jafari

Abstract:

The ionizing radiations cause different kinds of damages in electronic components. MOSFETs, most common transistors in today’s digital and analog circuits, are severely sensitive to TID damage. In this work, the threshold voltage shift of CD4007 device, which is an integrated circuit including P-channel and N-channel MOS transistors, was investigated for low dose gamma irradiation under different gate bias voltages. We used linear extrapolation method to extract threshold voltage from ID-VG characteristic curve. The results showed that the threshold voltage shift was approximately 27.5 mV/Gy for N-channel and 3.5 mV/Gy for P-channel transistors at the gate bias of |9 V| after irradiation by Co-60 gamma ray source. Although the sensitivity of the devices under test were strongly dependent to biasing condition and transistor type, the threshold voltage shifted linearly versus accumulated dose in all cases. The overall results show that the application of CD4007 as an electronic buffer in a radiation therapy system is limited by TID damage. However, this integrated circuit can be used as a cheap and sensitive radiation dosimeter for accumulated dose measurement in radiation therapy systems.

Keywords: Threshold voltage shift, MOS transistor, linear extrapolation, gamma irradiation.

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1191 A ±0.5V BiCMOS Class-A Current Conveyor

Authors: Subodh Thankachan, Manisha Pattanaik, S. S. Rajput

Abstract:

In this paper, a new BiCMOS CCII and CCCII, capable of operate at ±0.5V and having wide dynamic range with achieved bandwidth of 480MHz and 430MHz respectively have been proposed. The structures have been found to be insensitive to the threshold voltage variations. The proposed circuits are suitable for implementation using 0.25μm BiCMOS technology. Pspice simulations confirm the performance of the proposed structures.

Keywords: BiCMOS, Current conveyor, Compound current conveyor, Low supply voltage, Threshold voltage variation.

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1190 A High Precision Temperature Insensitive Current and Voltage Reference Generator

Authors: Kimberly Jane S. Uy, Patricia Angela Reyes-Abu, Wen Yaw Chung

Abstract:

A high precision temperature insensitive current and voltage reference generator is presented. It is specifically developed for temperature compensated oscillator. The circuit, designed using MXIC 0.5um CMOS technology, has an operating voltage that ranges from 2.6V to 5V and generates a voltage of 1.21V and a current of 6.38 ӴA. It exhibits a variation of ±0.3nA for the current reference and a stable output for voltage reference as the temperature is varied from 0°C to 70°C. The power supply rejection ratio obtained without any filtering capacitor at 100Hz and 10MHz is -30dB and -12dB respectively.

Keywords: Current reference, voltage reference, threshold voltage, temperature compensation, mobility.

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1189 The Design of PFM Mode DC-DC Converter with DT-CMOS Switch

Authors: Jae-Chang Kwak, Yong-Seo Koo

Abstract:

The high efficiency power management IC (PMIC) with switching device is presented in this paper. PMIC is controlled with PFM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS (DT-CMOS) with low on-resistance is designed to decrease conduction loss. The threshold voltage of DT-CMOS drops as the gate voltage increase, resulting in a much higher current handling capability than standard MOSFET. PFM control circuits consist of a generator, AND gate and comparator. The generator is made to have 1.2MHz oscillation voltage. The DC-DC converter based on PFM control circuit and low on-resistance switching device is presented in this paper.

Keywords: DT-CMOS, PMIC, PFM, DC-DC converter.

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1188 Design and Characterization of a CMOS Process Sensor Utilizing Vth Extractor Circuit

Authors: Rohana Musa, Yuzman Yusoff, Chia Chieu Yin, Hanif Che Lah

Abstract:

This paper presents the design and characterization of a low power Complementary Metal Oxide Semiconductor (CMOS) process sensor. The design is targeted for implementation using Silterra’s 180 nm CMOS process technology. The proposed process sensor employs a voltage threshold (Vth) extractor architecture for detection of variations in the fabrication process. The process sensor generates output voltages in the range of 401 mV (fast-fast corner) to 443 mV (slow-slow corner) at nominal condition. The power dissipation for this process sensor is 6.3 µW with a supply voltage of 1.8V with a silicon area of 190 µm X 60 µm. The preliminary result of this process sensor that was fabricated indicates a close resemblance between test and simulated results.

Keywords: CMOS Process sensor, Process, Voltage and Temperature (PVT) sensor, threshold extractor circuit, Vth extractor circuit.

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1187 Vertical Silicon Nanowire MOSFET With A Fully-Silicided (FUSI) NiSi2 Gate

Authors: Z. X. Chen, N. Singh, D.-L. Kwong

Abstract:

This paper presents a vertical silicon nanowire n- MOSFET integrated with a CMOS-compatible fully-silicided (FUSI) NiSi2 gate. Devices with nanowire diameter of 50nm show good electrical performance (SS < 70mV/dec, DIBL < 30mV/V, Ion/Ioff > 107). Most significantly, threshold voltage tunability of about 0.2V is shown. Although threshold voltage remains low for the 50nm diameter device, it is expected to become more positive as nanowire diameter reduces.

Keywords: NiSi , fully-silicided (FUSI) gate, vertical siliconnanowire (SiNW), CMOS compatible.

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1186 Impact of Height of Silicon Pillar on Vertical DG-MOSFET Device

Authors: K. E. Kaharudin, A. H. Hamidon, F. Salehuddin

Abstract:

Vertical Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is believed to suppress various short channel effect problems. The gate to channel coupling in vertical DG-MOSFET are doubled, thus resulting in higher current density. By having two gates, both gates are able to control the channel from both sides and possess better electrostatic control over the channel. In order to ensure that the transistor possess a superb turn-off characteristic, the subs-threshold swing (SS) must be kept at minimum value (60-90mV/dec). By utilizing SILVACO TCAD software, an n-channel vertical DG-MOSFET was successfully designed while keeping the sub-threshold swing (SS) value as minimum as possible. From the observation made, the value of sub-threshold swing (SS) was able to be varied by adjusting the height of the silicon pillar. The minimum value of sub-threshold swing (SS) was found to be 64.7mV/dec with threshold voltage (VTH) of 0.895V. The ideal height of the vertical DG-MOSFET pillar was found to be at 0.265 µm.

Keywords: DG-MOSFET, pillar, SCE, vertical

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1185 Modification of Electrical and Switching Characteristics of a Non Punch-Through Insulated Gate Bipolar Transistor by Gamma Irradiation

Authors: Hani Baek, Gwang Min Sun, Chansun Shin, Sung Ho Ahn

Abstract:

Fast neutron irradiation using nuclear reactors is an effective method to improve switching loss and short circuit durability of power semiconductor (insulated gate bipolar transistors (IGBT) and insulated gate transistors (IGT), etc.). However, not only fast neutrons but also thermal neutrons, epithermal neutrons and gamma exist in the nuclear reactor. And the electrical properties of the IGBT may be deteriorated by the irradiation of gamma. Gamma irradiation damages are known to be caused by Total Ionizing Dose (TID) effect and Single Event Effect (SEE), Displacement Damage. Especially, the TID effect deteriorated the electrical properties such as leakage current and threshold voltage of a power semiconductor. This work can confirm the effect of the gamma irradiation on the electrical properties of 600 V NPT-IGBT. Irradiation of gamma forms lattice defects in the gate oxide and Si-SiO2 interface of the IGBT. It was confirmed that this lattice defect acts on the center of the trap and affects the threshold voltage, thereby negatively shifted the threshold voltage according to TID. In addition to the change in the carrier mobility, the conductivity modulation decreases in the n-drift region, indicating a negative influence that the forward voltage drop decreases. The turn-off delay time of the device before irradiation was 212 ns. Those of 2.5, 10, 30, 70 and 100 kRad(Si) were 225, 258, 311, 328, and 350 ns, respectively. The gamma irradiation increased the turn-off delay time of the IGBT by approximately 65%, and the switching characteristics deteriorated.

Keywords: NPT-IGBT, gamma irradiation, switching, turn-off delay time, recombination, trap center.

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1184 Dynamic Variation in Nano-Scale CMOS SRAM Cells Due to LF/RTS Noise and Threshold Voltage

Authors: M. Fadlallah, G. Ghibaudo, C. G. Theodorou

Abstract:

The dynamic variation in memory devices such as the Static Random Access Memory can give errors in read or write operations. In this paper, the effect of low-frequency and random telegraph noise on the dynamic variation of one SRAM cell is detailed. The effect on circuit noise, speed, and length of time of processing is examined, using the Supply Read Retention Voltage and the Read Static Noise Margin. New test run methods are also developed. The obtained results simulation shows the importance of noise caused by dynamic variation, and the impact of Random Telegraph noise on SRAM variability is examined by evaluating the statistical distributions of Random Telegraph noise amplitude in the pull-up, pull-down. The threshold voltage mismatch between neighboring cell transistors due to intrinsic fluctuations typically contributes to larger reductions in static noise margin. Also the contribution of each of the SRAM transistor to total dynamic variation has been identified.

Keywords: Low-frequency noise, Random Telegraph Noise, Dynamic Variation, SRRV.

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1183 Modeling and Simulation of Dynamic Voltage Restorer for Mitigation of Voltage Sags

Authors: S. Ganesh, L. Raguraman, E. Anushya, J. krishnasree

Abstract:

Voltage sags are the most common power quality disturbance in the distribution system. It occurs due to the fault in the electrical network or by the starting of a large induction motor and this can be solved by using the custom power devices such as Dynamic Voltage Restorer (DVR). In this paper DVR is proposed to compensate voltage sags on critical loads dynamically. The DVR consists of VSC, injection transformers, passive filters and energy storage (lead acid battery). By injecting an appropriate voltage, the DVR restores a voltage waveform and ensures constant load voltage. The simulation and experimental results of a DVR using MATLAB software shows clearly the performance of the DVR in mitigating voltage sags.

Keywords: Dynamic voltage restorer, Voltage sags, Power quality, Injection methods.

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1182 Low Voltage High Gain Linear Class AB CMOS OTA with DC Level Input Stage

Authors: Houda Bdiri Gabbouj, Néjib Hassen, Kamel Besbes

Abstract:

This paper presents a low-voltage low-power differential linear transconductor with near rail-to-rail input swing. Based on the current-mirror OTA topology, the proposed transconductor combines the Flipped Voltage Follower (FVF) technique to linearize the transconductor behavior that leads to class- AB linear operation and the virtual transistor technique to lower the effective threshold voltages of the transistors which offers an advantage in terms of low supply requirement. Design of the OTA has been discussed. It operates at supply voltages of about ±0.8V. Simulation results for 0.18μm TSMC CMOS technology show a good input range of 1Vpp with a high DC gain of 81.53dB and a total harmonic distortion of -40dB at 1MHz for an input of 1Vpp. The main aim of this paper is to present and compare new OTA design with high transconductance, which has a potential to be used in low voltage applications.

Keywords: Amplifier class AB, current mirror, flipped voltage follower, low voltage.

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1181 Lookup Table Reduction and Its Error Analysis of Hall Sensor-Based Rotation Angle Measurement

Authors: Young-San Shin, Seongsoo Lee

Abstract:

Hall sensor is widely used to measure rotation angle. When the Hall voltage is measured for linear displacement, it is converted to angular displacement using arctangent function, which requires a large lookup table. In this paper, a lookup table reduction technique is presented for angle measurement. When the input of the lookup table is small within a certain threshold, the change of the outputs with respect to the change of the inputs is relatively small. Thus, several inputs can share same output, which significantly reduce the lookup table size. Its error analysis was also performed, and the threshold was determined so as to maintain the error less than 1°. When the Hall voltage has 11-bit resolution, the lookup table size is reduced from 1,024 samples to 279 samples.

Keywords: Hall sensor, angle measurement, lookup table, arctangent.

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1180 Breakdown of LDPE Film under Heavy Water Absorption

Authors: Eka PW, T. Okazaki, Y. Murakami, N., Hozumi, M. Nagao

Abstract:

The breakdown strength characteristic of Low Density Polyethylene films (LDPE) under DC voltage application and the effect of water absorption have been studied. Mainly, our experiment was investigated under two conditions; dry and heavy water absorption. Under DC ramp voltage, the result found that the breakdown strength under heavy water absorption has a lower value than dry condition. In order to clarify the effect, the temperature rise of film was observed using non contact thermograph until the occurrence of the electrical breakdown and the conduction current of the sample was also measured in correlation with the thermograph measurement. From the observations, it was shown that under the heavy water absorption, the hot spot in the samples appeared at lower voltage. At the same voltage the temperature of the hot spot and conduction current was higher than that under the dry condition. The measurement result has a good correlation between the existence of a critical field for conduction current and thermograph observation. In case of the heavy water absorption, the occurrence of the threshold field was earlier than the dry condition as result lead to higher of conduction current and the temperature rise appears after threshold field was significantly increased in increasing of field. The higher temperature rise was caused by the higher current conduction as the result the insulation leads to breakdown to the lower field application.

Keywords: Low density polyethylene, heavy water absorption, conduction current, temperature rise.

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1179 Artificial Voltage-Controlled Capacitance and Inductance using Voltage-Controlled Transconductance

Authors: Mansour I. Abbadi, Abdel-Rahman M. Jaradat

Abstract:

In this paper, a technique is proposed to implement an artificial voltage-controlled capacitance or inductance which can replace the well-known varactor diode in many applications. The technique is based on injecting the current of a voltage-controlled current source onto a fixed capacitor or inductor. Then, by controlling the transconductance of the current source by an external bias voltage, a voltage-controlled capacitive or inductive reactance is obtained. The proposed voltage-controlled reactance devices can be designed to work anywhere in the frequency spectrum. Practical circuits for the proposed voltage-controlled reactances are suggested and simulated.

Keywords: voltage-controlled capacitance, voltage-controlled inductance, varactor diode, variable transconductance.

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1178 Static Voltage Stability Margin Enhancement Using SVC and TCSC

Authors: Mohammed Amroune, Hadi Sebaa, Tarek Bouktir

Abstract:

Reactive power limit of power system is one of the major causes of voltage instability. The only way to save the system from voltage instability is to reduce the reactive power load or add additional reactive power to reaching the point of voltage collapse. In recent times, the application of FACTS devices is a very effective solution to prevent voltage instability due to their fast and very flexible control. In this paper, voltage stability assessment with SVC and TCSC devices is investigated and compared in the modified IEEE 30-bus test system. The fast voltage stability indicator (FVSI) is used to identify weakest bus and to assess the voltage stability of power system.

Keywords: SVC, TCSC, Voltage stability, Fast Voltage Stability Index (FVSI), Reactive power.

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1177 SCR-Based Advanced ESD Protection Device for Low Voltage Application

Authors: Bo Bae Song, Byung Seok Lee, Hyun Young Kim, Chung Kwang Lee, Yong Seo Koo

Abstract:

This paper proposed a silicon controller rectifier (SCR) based ESD protection device to protect low voltage ESD for integrated circuit. The proposed ESD protection device has low trigger voltage and high holding voltage compared with conventional SCR-based ESD protection devices. The proposed ESD protection circuit is verified and compared by TCAD simulation. This paper verified effective low voltage ESD characteristics with low trigger voltage of 5.79V and high holding voltage of 3.5V through optimization depending on design variables (D1, D2, D3 and D4).

Keywords: ESD, SCR, Holding voltage, Latch-up.

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1176 Characterization of Electrohydrodynamic Force on Dielectric-Barrier-Discharge Plasma Actuator Using Fluid Simulation

Authors: Hiroyuki Nishida, Taku Nonomura, Takashi Abe

Abstract:

Wall-surface jet induced by the dielectric barrier discharge (DBD) has been proposed as an actuator for active flow control in aerodynamic applications. Discharge plasma evolution of the DBD plasma actuator was simulated based on a simple fluid model, in which the electron, one type of positive ion and negative ion were taken into account. Two-dimensional simulation was conducted, and the results are in agreement with the insights obtained from experimental studies. The simulation results indicate that the discharge mode changes depending on applied voltage slope; when the applied voltage is positive-going with high applied voltage slope, the corona-type discharge mode turns into the streamer-type discharge mode and the threshold voltage slope is around 300 kV/ms in this simulation. The characteristics of the electrohydrodynamic (EHD) force, which is the source of the wall-surface jet, also change depending on the discharge mode; the tentative peak value of the EHD force during the positive-going voltage phase is saturated by the periodical formation of the streamer-type discharge.

Keywords: Dielectric barrier discharge, Plasma actuator, Fluid simulation.

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1175 An Analytical Comparison between Open Loop, PID and Fuzzy Logic Based DC-DC Boost Convertor

Authors: Muhammad Mujtaba Asad, Razali Bin Hassan, Fahad Sherwani

Abstract:

This paper explains about the voltage output for DC to DC boost converter between open loop, PID controller and fuzzy logic controller through Matlab Simulink. Simulink input voltage was set at 12V and the voltage reference was set at 24V. The analysis on the deviation of voltage resulted that the difference between reference voltage setting and the output voltage is always lower. Comparison between open loop, PID and FLC shows that, the open loop circuit having a bit higher on the deviation of voltage. The PID circuit boosts for FLC has a lesser deviation of voltage and proved that it is such a better performance on control the deviation of voltage during the boost mode.

Keywords: Boost Convertors, Power Electronics, PID, Fuzzy logic, Open loop.

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1174 A Study on ESD Protection Circuit Applying Silicon Controlled Rectifier-Based Stack Technology with High Holding Voltage

Authors: Hee-Guk Chae, Bo-Bae Song, Kyoung-Il Do, Jeong-Yun Seo, Yong-Seo Koo

Abstract:

In this study, an improved Electrostatic Discharge (ESD) protection circuit with low trigger voltage and high holding voltage is proposed. ESD has become a serious problem in the semiconductor process because the semiconductor density has become very high these days. Therefore, much research has been done to prevent ESD. The proposed circuit is a stacked structure of the new unit structure combined by the Zener Triggering (SCR ZTSCR) and the High Holding Voltage SCR (HHVSCR). The simulation results show that the proposed circuit has low trigger voltage and high holding voltage. And the stack technology is applied to adjust the various operating voltage. As the results, the holding voltage is 7.7 V for 2-stack and 10.7 V for 3-stack.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage.

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1173 Technique for Voltage Control in Distribution System

Authors: S. Thongkeaw, M. Boonthienthong

Abstract:

This paper presents the techniques for voltage control in distribution system. It is integrated in the distribution management system. Voltage is an important parameter for the control of electrical power systems. The distribution network operators have the responsibility to regulate the voltage supplied to consumer within statutory limits. Traditionally, the On-Load Tap Changer (OLTC) transformer equipped with automatic voltage control (AVC) relays is the most popular and effective voltage control device. A static synchronous compensator (STATCOM) may be equipped with several controllers to perform multiple control functions. Static Var Compensation (SVC) is regulation slopes and available margins for var dispatch. The voltage control in distribution networks is established as a centralized analytical function in this paper. 

Keywords: Voltage Control, Reactive Power, Distribution System.

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1172 Noise-Improved Signal Detection in Nonlinear Threshold Systems

Authors: Youguo Wang, Lenan Wu

Abstract:

We discuss the signal detection through nonlinear threshold systems. The detection performance is assessed by the probability of error Per . We establish that: (1) when the signal is complete suprathreshold, noise always degrades the signal detection both in the single threshold system and in the parallel array of threshold devices. (2) When the signal is a little subthreshold, noise degrades signal detection in the single threshold system. But in the parallel array, noise can improve signal detection, i.e., stochastic resonance (SR) exists in the array. (3) When the signal is predominant subthreshold, noise always can improve signal detection and SR always exists not only in the single threshold system but also in the parallel array. (4) Array can improve signal detection by raising the number of threshold devices. These results extend further the applicability of SR in signal detection.

Keywords: Probability of error, signal detection, stochasticresonance, threshold system.

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1171 Multi-threshold Approach for License Plate Recognition System

Authors: Siti Norul Huda Sheikh Abdullah, Farshid Pirahan Siah, Nor Hanisah Haji Zainal Abidin, Shahnorbanun Sahran

Abstract:

The objective of this paper is to propose an adaptive multi threshold for image segmentation precisely in object detection. Due to the different types of license plates being used, the requirement of an automatic LPR is rather different for each country. The proposed technique is applied on Malaysian LPR application. It is based on Multi Layer Perceptron trained by back propagation. The proposed adaptive threshold is introduced to find the optimum threshold values. The technique relies on the peak value from the graph of the number object versus specific range of threshold values. The proposed approach has improved the overall performance compared to current optimal threshold techniques. Further improvement on this method is in progress to accommodate real time system specification.

Keywords: Multi-threshold approach, license plate recognition system.

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1170 Threshold Stress of the Soil Subgrade Evaluation for Highway Formations

Authors: Elsa Eka Putri, N.S.V Kameswara Rao, M. A. Mannan

Abstract:

The objective of this study is to evaluate the threshold stress of the clay with sand subgrade soil. Threshold stress can be defined as the stress level above which cyclic loading leads to excessive deformation and eventual failure. The thickness determination of highways formations using the threshold stress approach is a more realistic assessment of the soil behaviour because it is subjected to repeated loadings from moving vehicles. Threshold stress can be evaluated by plastic strain criterion, which is based on the accumulated plastic strain behaviour during cyclic loadings [1]. Several conditions of the all-round pressure the subgrade soil namely, zero confinement, low all-round pressure and high all-round pressure are investigated. The threshold stresses of various soil conditions are determined. Threshold stress of the soil are 60%, 31% and 38.6% for unconfined partially saturated sample, low effective stress saturated sample, high effective stress saturated sample respectively.

Keywords: threshold stress, cyclic loading, pore water pressure.

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1169 A Study on Unidirectional Analog Output Voltage Inverter for Capacitive Load

Authors: Sun-Ki Hong, Nam-HeeByeon, Jung-Seop Lee, Tae-Sam Kang

Abstract:

For Common R or R-L load to apply arbitrary voltage, the bridge traditional inverters don’t have any difficulties by PWM method. However for driving some piezoelectric actuator, arbitrary voltage not a pulse but a steady voltage should be applied. Piezoelectric load is considered as R-C load and its voltage does not decrease even though the applied voltage decreases. Therefore it needs some special inverter with circuit that can discharge the capacitive energy. Especially for unidirectional arbitrary voltage driving like as sine wave, it becomes more difficult problem. In this paper, a charge and discharge circuit for unidirectional arbitrary voltage driving for piezoelectric actuator is proposed. The circuit has charging and discharging switches for increasing and decreasing output voltage. With the proposed simple circuit, the load voltage can have any unidirectional level with tens of bandwidth because the load voltage can be adjusted by switching the charging and discharging switch appropriately. The appropriateness is proved from the simulation of the proposed circuit.

Keywords: DC-DC converter, analog output voltage, sinusoidal drive, piezoelectric load, discharging circuit.

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1168 Threshold Submergence of Flow over PK Weirs

Authors: A. Javaheri, A. R. Kabiri-Samani

Abstract:

In this study an extensive experimental research is carried out to develop a better understanding of the effects of Piano Key (PK) weir geometry on weir flow threshold submergence. Experiments were conducted in a 12 m long, 0.4 m wide and 0.7 m deep rectangular glass wall flume. The main objectives were to investigate the effect of the PK weir geometries including the weir length, weir height, inlet-outlet key widths, upstream and downstream apex overhangs, and slopped floors on threshold submergence and study the hydraulic flow characteristics. From the experimental results, a practical formula is proposed to evaluate the flow threshold submergence over PK weirs.

Keywords: Model experimentation, flow characteristics, Piano Key weir, threshold submergence.

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1167 SCR-Stacking Structure with High Holding Voltage for I/O and Power Clamp

Authors: Hyun-Young Kim, Chung-Kwang Lee, Han-Hee Cho, Sang-Woon Cho, Yong-Seo Koo

Abstract:

In this paper, we proposed a novel SCR (Silicon Controlled Rectifier) - based ESD (Electrostatic Discharge) protection device for I/O and power clamp. The proposed device has a higher holding voltage characteristic than conventional SCR. These characteristics enable to have latch-up immunity under normal operating conditions as well as superior full chip ESD protection. The proposed device was analyzed to figure out electrical characteristics and tolerance robustness in term of individual design parameters (D1, D2, D3). They are investigated by using the Synopsys TCAD simulator. As a result of simulation, holding voltage increased with different design parameters. The holding voltage of the proposed device changes from 3.3V to 7.9V. Also, N-Stack structure ESD device with the high holding voltage is proposed. In the simulation results, 2-stack has holding voltage of 6.8V and 3-stack has holding voltage of 10.5V. The simulation results show that holding voltage of stacking structure can be larger than the operation voltage of high-voltage application.

Keywords: ESD, SCR, holding voltage, stack, power clamp.

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1166 Analysis of SCR-Based ESD Protection Circuit on Holding Voltage Characteristics

Authors: Yong Seo Koo, Jong Ho Nam, Yong Nam Choi, Dae Yeol Yoo, Jung Woo Han

Abstract:

This paper presents a silicon controller rectifier (SCR) based ESD protection circuit for IC. The proposed ESD protection circuit has low trigger voltage and high holding voltage compared with conventional SCR ESD protection circuit. Electrical characteristics of the proposed ESD protection circuit are simulated and analyzed using TCAD simulator. The proposed ESD protection circuit verified effective low voltage ESD characteristics with low trigger voltage and high holding voltage.

Keywords: ESD (Electro-Static Discharge), SCR (Silicon Controlled Rectifier), holding Voltage.

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1165 On the Reliability of Low Voltage Network with Small Scale Distributed Generators

Authors: Rade M. Ciric, Nikola Lj.Rajakovic

Abstract:

Since the 80s huge efforts have been made to utilize renewable energy sources to generate electric power. This paper reports some aspects of integration of the distributed generators into the low voltage distribution networks. An assessment of impact of the distributed generators on the reliability indices of low voltage network is performed. Results obtained from case study using low voltage network, are presented and discussed.

Keywords: low voltage network, distributed generation, reliability indices

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