Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 30114
Design of High Gain, High Bandwidth Op-Amp for Reduction of Mismatch Currents in Charge Pump PLL in 180 nm CMOS Technology

Authors: R .H. Talwekar, S. S Limaye

Abstract:

The designing of charge pump with high gain Op- Amp is a challenging task for getting faithful response .Design of high performance phase locked loop require ,a design of high performance charge pump .We have designed a operational amplifier for reducing the error caused by high speed glitch in a transistor and mismatch currents . A separate Op-Amp has designed in 180 nm CMOS technology by CADENCE VIRTUOSO tool. This paper describes the design of high performance charge pump for GHz CMOS PLL targeting orthogonal frequency division multiplexing (OFDM) application. A high speed low power consumption Op-Amp with more than 500 MHz bandwidth has designed for increasing the speed of charge pump in Phase locked loop.

Keywords: Charge pump (CP) Orthogonal frequency divisionmultiplexing (OFDM), Phase locked loop (PLL), Phase frequencydetector (PFD), Voltage controlled oscillator (VCO),

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1057231

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 3000

References:


[1] O. Jung-Yu Chang, Che-Wei Fan, and Shen-Iuan Liu "A frequency Synthesizer for Mode-1 MB- OFDM UWB Application", National Taiwan University, Taipei Taiwan, 978-1-4244-2782-6/09/$25.00 ┬®2009 IEEE
[2] G. N. Lu and G. Sou,"A CMOS Op-Amp using a regulated-cascode transimpedance building block for high-gain, low-voltage achievement", 1997 IEEE International Symposiiini on Circuits aid Systems, June 9-12, 1997, Hong Kong
[3] Tian Xia*, Stephen Wyatt, " High Output Resistance and Wide Swing Voltage Charge Pump Circuit" , 9th International Symposium on Quality Electronic Design, 0-7695-3117-2/08 $25.00 ┬® 2008 IEEE
[4] Behzad Razavi. "Design of Analog CMOS integrated circuits",TMH Edition 2002
[5] Krzysztof Iniewski1, Sebastian Magierowski2, and Marek Syrzycki1 " Phase Locked Loop Gain shiping For Gigaheart", OPERATION" ISCAS2004
[6] Shan feng Cheng, Jose Silva-Martinez "Design and Analysis of an Ultrahigh-Speed Glitch-Free Fully deferential Charge Pump With Minimum Output Current Variation and Accurate Matching" , IEEE Transactions on Circuits and systems - II : Express Briefs, VOL. 53,NO. 9, September 2006
[7] Rania H. Mekky 1 and Mohamed Dessouky 1, 21 Mentor Graphic Egypt, Cairo, Egypt, "Design of low mismatch gain boosting Charge Pump circuit for Phase Locked Loop", IEEE ICM - December 2007
[8] Jianzheng Zhou 1, 2 Zhigong Wang 1*, "A High- Performance CMOS.Charge-Pump for Phase-Locked Loops", ICMMT2008 Proceedings, 978-1-4244-1880-0/08/$25.00 ┬®2008 IEEE.
[9] Brian Daniels and Ronan Farrell, " Stability Analysis Of High Frequency Digital Phase Locked Loops using Piecewise Linear Model", ISSC 2006, Dublin Institute of Technology, June 28-30
[10] A. Pugliese, G. Cappuccino and G. Cocorullo, "Nested Miller compensation capacitor sizing rules for fast-settling amplifier design", ELECTRONICS LETTERS 12th May 2005 Vol. 41 No. 10
[11] M.-S. Hwang, J. Kim and D.-K. Jeong, "Reduction of pump current mismatch in charge-pump PLL", ELECTRONICS LETTERS 29th January 2009 Vol. 45 No. 3
[12] Phillip E Allen & Douglas R Holberg, "CMOS Analog Circuit Design", Second Edition Oxford University Press
[13] H Md Shuaeb Fazeel Leneesh Raghavan, "Reduction of Current Mismatch in PLL Charge Pump", 2009 IEEE Computer Society Annual Symposium on VLSI.