P.K. Sharma and  B. Bhargava and  S. Akashe,  Reduction of Leakage Power in Digital Logic Circuits Using Stacking Technique in 45 Nanometer Regime.   journal   = {International Journal of Electronics and Communication Engineering}, [online]. World Academy of Science, Engineering and Technology.
    October 2013, vol. 73(1). 60 - 65
    [viewed 23 April 2024]. Available from: https://publications.waset.org/pdf/17356.