Ankit Mitra,  Design and Analysis of a Low Power High Speed 1 Bit Full Adder Cell Based On TSPC Logic with Multi-Threshold CMOS.   journal   = {International Journal of Electrical and Computer Engineering}, [online]. World Academy of Science, Engineering and Technology.
    February 2014, vol. 85(1). 185 - 188
    [viewed 24 April 2024]. Available from: https://publications.waset.org/pdf/9997712.