Subthreshold Circuit Performance Investigation under Temperature Variations

Authors: Mohd. Hasan, Ajmal Kafeel, S. D. Pable

Abstract:

Ultra-low-power (ULP) circuits have received widespread attention due to the rapid growth of biomedical applications and Battery-less Electronics. Subthreshold region of transistor operation is used in ULP circuits. Major research challenge in the subthreshold operating region is to extract the ULP benefits with minimal degradation in speed and robustness. Process, Voltage and Temperature (PVT) variations significantly affect the performance of subthreshold circuits. Designed performance parameters of ULP circuits may vary largely due to temperature variations. Hence, this paper investigates the effect of temperature variation on device and circuit performance parameters at different biasing voltages in the subthreshold region. Simulation results clearly demonstrate that in deep subthreshold and near threshold voltage regions, performance parameters are significantly affected whereas in moderate subthreshold region, subthreshold circuits are more immune to temperature variations. This establishes that moderate subthreshold region is ideal for temperature immune circuits.

Keywords: Subthreshold, temperature variations, ultralow power.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1330263

References:

[1] G.E.Moore, "Cramming more components onto integrated circuits," in Electronics, vol.38, no.8, pp. 4, April 1965.
[2] Nam Sung Kim, K.Flautner, D. Blaauw, and T.Mudge, "Circuit and micro archirectural techniques for reducing cache leakage power," IEEE Trans. on VLSI system, vol. 12, no.2, pp. 167-187, Feb. 2004.
[3] Fei Li, Yan Lin, and Lei He, "Field programmability of supply voltages for FPGA power reduction," IEEE Trans. on Computer-Aided Design of Integrated Citcuits and System, vol.26, No.4, pp. 752-764, April 2007.
[4] Jason H. Anderson and Farid N. Najim, "Low-power programmable FPGA routing circuitry," IEEE Trans. on VLSI systems, vol. 17, no.8, pp. 1048-1060, August 2009.
[5] Alicewang, Benton Calhoun, Anantha P.Chandrakasan, Sub-threshold design for ultra low-Power systems, Springer publication. 2006.
[6] Bipul C.Paul, Amit Agarwal and Kaushik Roy, "Low -power design techniques for scaled technologies," INTEGRATION, the VLSI journal , vol.39, page. 64-89, March 2006.
[7] Hendrawan Soeleman, Kaushik Roy and Bipul C.Paul, Robust subthreshold logic for ultralow power operation, IEEE Transactions on Very Large Scale Integration (VLSI) System, vol. 9, no. 1, pp. 90-99, Feb. 2001.
[8] Dejan Markovic, Cheng C. Wang, Louis P.Alarcon, Tsung-Te Liu, and Jan M. Rabaey, "Ultralow-power design in near-threshold region," in proceedings of the IEEE, vol.98, no.2, page. 237-252, February 2010.
[9] Sumeet kumar Gupta, Arijit Raychowdhury, Kaushik Roy, Digital computation in subthreshold region for ultra-low-power operation: A device-circuit-architecture codesign perspective, in Proc.of the IEEE, vol. 98, no. 2, pp. 160-190, Feb. 2010.
[10] B.H.Calhoun, J.F.Ryan, Sudhanshu Khanna, Mateja Putic and John Lach, Flexible circuits and architecture for ultralow power, in Proceeding of the IEEE, vol. 98, no. 2, pp. 167-282, Feb. 2010.
[11] S.D.Pable and Mohd.Hasan, "High speed interconnect through device optimization for subthreshold FPGA," Microelectronics Journal, vol. 42 no. 3, page. 545-552, January 2011.
[12] Jan M.Rabaey, Anantha Chandrakasan, Borivoje Nikolic, Digital integrated Circuits- A Design perspective, Pearson Education, 2nd Edition, 2007.
[13] Basab Datta and Wayne Burleson, " Temperature effects on energy optimization in subthreshold circuit design," 10th International Symposium on Quality Electronic Design, pp. 680-685, 2009.
[14] S. D. Pable and Mohd. Hasan, "Ultralow-Power Signaling Challenges for Subthreshold Global Interconnects," INTEGRATION, the VLSI Journal, Elsevier Science Publishers B. V, Vol. (42), pp. 186-196, Sep. 2011.