Search results for: Bipolar transistor

Authors: Yong-Seo Koo, Jin-Woo Jung, Byung-Seok Lee, Dong-Su Kim, Yil-Suk Yang

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In this paper, a novel LVTSCR-based device for electrostatic discharge (ESD) protection of integrated circuits (ICs) is designed, fabricated and characterized. The proposed device is similar to the conventional LVTSCR but it has an embedded PMOSFET in the anode n-well to enhance the turn on speed, the clamping capability and the robustness. This is possible because the embedded PMOSFET provides the sub-path of ESD discharge current. The TLP, HBM and MM testing are carried out to verify the ESD performance of the proposed devices, which are fabricated in 0.35um (Bipolar-CMOS-DMOS) BCDMOS process. The device has the robustness of 70mA/um that is higher about 60mA/um than the LVTSCR, approximately.

Keywords: ESD Protection, grounded gate NMOS (GGNMOS), low trigger voltage SCR (LVTSCR)

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Authors: Hsin-Ping Huang, Shyankay Jou

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Resistive switching of aluminum nitride (AlN_x) thin film was demonstrated in a TaN/AlN_x/TiN memory cell that was prepared by sputter deposition techniques. The memory cell showed bipolar switching of resistance between +3.5 V and –3.5 V. The resistance ratio of high resistance state (HRS) to low resistance state (HRS), R_HRS/R_LRS, was about 2 over 100 cycles of endurance test. Both the LRS and HRS of the memory cell exhibited ohmic conduction at low voltages and Poole-Frenkel emission at high voltages. The electrical conduction in the TaN/AlN_x/TiN memory cell was possibly attributed to the interactions between charges and defects in the AlN_x film.

Keywords: Aluminum nitride, nonvolatile memory, resistive switching, thin films.

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Authors: P. Vaculik

Abstract:

The newest semiconductor devices on the market are MOSFET transistors based on the silicon carbide – SiC. This material has exclusive features thanks to which it becomes a better switch than Si – silicon semiconductor switch. There are some special features that need to be understood to enable the device’s use to its full potential. The advantages and differences of SiC MOSFETs in comparison with Si IGBT transistors have been described in first part of this article. Second part describes driver for SiC MOSFET transistor and last part of article represents SiC MOSFET in the application of buck converter (step-down) and design of simple RC snubber. 

Keywords: SiC, Si, MOSFET, IGBT, SBD, RC snubber.

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Authors: Makesh Iyer, T. Shanmuganantham

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This work deals with the designing of an efficient low noise amplifier for 10.00 GHz applications. The amplifier is designed using Gallium Arsenide High Electron Mobility Transistor (GaAs HEMT) ATF – 36077 with inductive source degeneration technique which is one of the techniques to improve the stability of the potentially unstable device and make it unconditionally stable. Also, different substrates are used for designing the LNA to identify the suitable substrate that gives optimum results. It is observed that the noise immunity is more in Low Noise Amplifier (LNA) designed using RT Duroid 5880 substrate. This design resulted in noise figure of 0.859 dB and power gain of 15.530 dB. The comparative analysis of the LNA design is discussed in this paper.

Keywords: Low noise amplifier, substrate, distributed components, gain, noise figure.

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Authors: S. Kampoosiri, S. Pojprapai, R. Yimnirunand, B. Marungsri

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Fatigue behaviors of Lead Zirconate Titanate (PZT) ceramics under different amplitude of bipolar electrical loads have been investigated. Fatigue behavior is represented by the change of hysteresis loops and remnant polarization. Three levels of electrical load amplitudes (1.00, 1.25 and 1.50 kV /mm) were applied in this experimental. It was found that the remnant polarization decreased significantly with the number of loading cycles. The degree of fatigue degradation depends on the amplitude of electric field. The higher amplitude exhibits the greater fatigue degradation.

Keywords: Lead Zirconate Titanate (PZT), hysteresis loop, Sawyer-Tower circuit, fatigue, polarization.

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Authors: Anwar H. Jarndal, Ahmed S. Elwakil

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In this paper, a fraction-order model for pad parasitic effect of GaN HEMT on Si substrate is developed and validated. Open de-embedding structure is used to characterize and de-embed substrate loading parasitic effects. Unbiased device measurements are implemented to extract parasitic inductances and resistances. The model shows very good simulation for S-parameter measurements under different bias conditions. It has been found that this approach can improve the simulation of intrinsic part of the transistor, which is very important for small- and large-signal modeling process.

Keywords: Fractional-order modeling, GaN HEMT, Si-substrate, open de-embedding structure.

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Authors: Yashvir Singh, Swati Chamoli

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In this paper, a power laterally-diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) on In_0.53Ga_0.47As is presented. The device utilizes a thicker field-oxide with low dielectric constant under the field-plate in order to achieve possible reduction in device capacitances and reduced-surface-field effect. Using 2D numerical simulations, performance of the proposed device is analyzed and compared with that of the conventional LDMOSFET. The proposed structure provides 50% increase in the breakdown voltage, 21% increase in transit frequency, and 72% improvement in figure-of-merit over the conventional device for same cell pitch.

Keywords: InGaAs, dielectric, lateral, power MOSFET.

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Authors: Ahmed El Oualkadi, Abdellah Ait Ouahman

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This paper discusses a systematic design of a Σ-Δ fractional-N Phase-Locked Loop based on HDL behavioral modeling. The proposed design consists in describing the mixed behavior of this PLL architecture starting from the specifications of each building block. The HDL models of critical PLL blocks have been described in VHDL-AMS to predict the different specifications of the PLL. The effect of different noise sources has been efficiently introduced to study the PLL system performances. The obtained results are compared with transistor-level simulations to validate the effectiveness of the proposed models for wireless applications in the frequency range around 2.45 GHz.

Keywords: Phase-locked loop, frequency synthesizer, fractional-N PLL, Σ-Δ modulator, HDL models

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Authors: Young Wook Lee, Sun-Jae Kim, Soo-Yeon Lee, Moon-Kyu Song, Woo-Geun Lee Min-Koo Han

Abstract:

We have fabricated a-IGZO TFT and investigated the stability under positive DC and AC bias stress. The threshold voltage of a-IGZO TFT shifts positively under those biases, and that reduces on-current. For this reason, conventional shift-register circuit employing TFTs which stressed by positive bias will be unstable, may do not work properly. We have designed a new 6-transistor shift-register, which has less transistors than prior circuits. The TFTs of the proposed shift-register are not suffering from positive DC or AC stress, mainly kept unbiased. Despite the compact design, the stable output signal was verified through the SPICE simulation even under RC delay of clock signal.

Keywords: Indium Gallium Zinc Oxide (IGZO), Thin FilmTransistor (TFT), shift-register

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Authors: Mojtaba Ghodsi, Hamidreza Ziaifar, Morteza Mohammadzaheri, Payam Soltani

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In this paper, the performance of a medium power (25 kW/25 kHz) hybrid inverter with a reactive transformer is investigated. To analyze the sensitivity of the inverster, the RSM technique is employed to manifest the effective factors in the inverter to minimize current passing through the Insulated Bipolar Gate Transistors (IGBTs) (current stress). It is revealed that the ratio of the axillary inductor to the effective inductance of resonant inverter (N), is the most effective parameter to minimize the current stress in this type of inverter. In practice, proper selection of N mitigates the current stress over IGBTs by five times. This reduction is very helpful to keep the IGBTs at normal temperatures.

Keywords: Analytical analysis, hybrid resonant inverter, reactive transformer, response surface method.

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Authors: Kyong-min Lee, Moon Soo Chang, PooGyeon Park

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In this paper, we propose a geometric modeling of illumination on the patterned image containing etching transistor. This image is captured by a commercial camera during the inspection of a TFT-LCD panel. Inspection of defect is an important process in the production of LCD panel, but the regional difference in brightness, which has a negative effect on the inspection, is due to the uneven illumination environment. In order to solve this problem, we present a geometric modeling of illumination consisting of an interpolation using the least squares method and 3D modeling using bezier surface. Our computational time, by using the sampling method, is shorter than the previous methods. Moreover, it can be further used to correct brightness in every patterned image.

Keywords: Bezier, defect, geometric modeling, illumination, inspection, LCD, panel.

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Authors: Doshi N. A., Dhobale S. B., Kakade S. R.

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As chip manufacturing technology is suddenly on the threshold of major evaluation, which shrinks chip in size and performance, LFSR (Linear Feedback Shift Register) is implemented in layout level which develops the low power consumption chip, using recent CMOS, sub-micrometer layout tools. Thus LFSR counter can be a new trend setter in cryptography and is also beneficial as compared to GRAY & BINARY counter and variety of other applications. This paper compares 3 architectures in terms of the hardware implementation, CMOS layout and power consumption, using Microwind CMOS layout tool. Thus it provides solution to a low power architecture implementation of LFSR in CMOS VLSI.

Keywords: Chip technology, Layout level, LFSR, Pass transistor

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Authors: Arafet Bouaicha, Hatem Allegui, Amar Rouane, El-Hassane Aglzim, Abdelkader Mami

Abstract:

In order to further understand the behavior of PEM fuel cell and optimize their performance, it is necessary to perform measurements in real time. The internal impedance measurement by electrochemical impedance spectroscopy (EIS) is of great importance. In this work, we present the impedance measurement method of a PEM fuel cell by electrochemical impedance spectroscopy method and the realization steps of electronic load for this measuring technique implementation. The theoretical results are obtained from the simulation of software PSPICE® and experimental tests are carried out using the Ballard Nexa™ PEM fuel cell system.

Keywords: Electronic load, MOS transistor, PEM fuel cell, Impedance measurement, Electrochemical Impedance Spectroscopy (EIS).

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Authors: Mehdi Saeidmanesh, Razali Ismail

Abstract:

Recently, Graphene Nanoribbon Field Effect Transistors (GNR FETs) attract a great deal of attention due to their better performance in comparison with conventional devices. In this paper, channel length Modulation (CLM) effect on the electrical characteristics of GNR FETs is analytically studied and modeled. To this end, the special distribution of the electric potential along the channel and current-voltage characteristic of the device is modeled. The obtained results of analytical model are compared to the experimental data of published works. As a result, it is observable that considering the effect of CLM, the current-voltage response of GNR FET is more realistic.

Keywords: Graphene nanoribbon, field effect transistors, short channel effects, channel length modulation.

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Authors: Mazhar B. Tayel, Amr H. Yassin

Abstract:

A proposed small-signal model parameters for a pseudomorphic high electron mobility transistor (PHEMT) is presented. Both extrinsic and intrinsic circuit elements of a smallsignal model are determined using genetic algorithm (GA) as a stochastic global search and optimization tool. The parameters extraction of the small-signal model is performed on 200-μm gate width AlGaAs/InGaAs PHEMT. The equivalent circuit elements for a proposed 18 elements model are determined directly from the measured S- parameters. The GA is used to extract the parameters of the proposed small-signal model from 0.5 up to 18 GHz.

Keywords: PHEMT, Genetic Algorithms, small signal modeling, optimization.

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Authors: Majed Omar Al-Dwairi

Abstract:

This paper evaluate the multilevel modulation for different techniques such as amplitude shift keying (M-ASK), MASK, differential phase shift keying (M-ASK-Bipolar), Quaternary Amplitude Shift Keying (QASK) and Quaternary Polarization-ASK (QPol-ASK) at a total bit rate of 107 Gbps. The aim is to find a costeffective very high speed transport solution. Numerical investigation was performed using Monte Carlo simulations. The obtained results indicate that some modulation formats can be operated at 100Gbps in optical communication systems with low implementation effort and high spectral efficiency.

Keywords: Optical communication, multilevel amplitude shift keying (M-ASK), Differential phase shift keying (DPSK), Quaternary Amplitude Shift Keying (QASK), Quaternary Polarization-ASK (QPol-ASK).

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Authors: W. Z. Wang, S. Todd, S. B. Dolmanan, K. B. Lee, L. Yuan, H. F. Sun, S. L. Selvaraj, M.Krishnakumar, G. Q. Lo, S. Tripathy

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The crystalline quality of the AlGaN/GaN high electron mobility transistor (HEMT) structure grown on a 200 mm silicon substrate has been investigated using UV-visible micro- Raman scattering and photoluminescence (PL). The visible Raman scattering probes the whole nitride stack with the Si substrate and shows the presence of a small component of residual in-plane stress in the thick GaN buffer resulting from a wafer bowing, while the UV micro-Raman indicates a tensile interfacial stress induced at the top GaN/AlGaN/AlN layers. PL shows a good crystal quality GaN channel where the yellow band intensity is very low compared to that of the near-band-edge transition. The uniformity of this sample is shown by measurements from several points across the epiwafer.

Keywords: Raman, photo luminescence, AlGaN/GaN, HEMT.

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Authors: Dorota Witkowska, Paweł Gosek, Lukasz Swiecicki, Wojciech Jernajczyk, Bruce J. West, Miroslaw Latka

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In clinical practice, the selection of an antidepressant often degrades to lengthy trial-and-error. In this work we employ a normalized wavelet power of alpha waves as a biomarker of antidepressant treatment response. This novel EEG metric takes into account both non-stationarity and intersubject variability of alpha waves. We recorded resting, 19-channel EEG (closed eyes) in 22 inpatients suffering from unipolar (UD, n=10) or bipolar (BD, n=12) depression. The EEG measurement was done at the end of the short washout period which followed previously unsuccessful pharmacotherapy. The normalized alpha wavelet power of 11 responders was markedly different than that of 11 nonresponders at several, mostly temporoparietal sites. Using the prediction of treatment response based on the normalized alpha wavelet power, we achieved 81.8% sensitivity and 81.8% specificity for channel T4.

Keywords: Alpha waves, antidepressant, treatment outcome, wavelet.

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Authors: H. Daoud Dammak, S. Bensalem, S. Zouari, M. Loulou

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This paper presents an optimized methodology to folded cascode operational transconductance amplifier (OTA) design. The design is done in different regions of operation, weak inversion, strong inversion and moderate inversion using the gm/ID methodology in order to optimize MOS transistor sizing. Using 0.35μm CMOS process, the designed folded cascode OTA achieves a DC gain of 77.5dB and a unity-gain frequency of 430MHz in strong inversion mode. In moderate inversion mode, it has a 92dB DC gain and provides a gain bandwidth product of around 69MHz. The OTA circuit has a DC gain of 75.5dB and unity-gain frequency limited to 19.14MHZ in weak inversion region.

Keywords: CMOS IC design, Folded Cascode OTA, gm/ID methodology, optimization.

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Authors: Po-Hsieh Lin, Jyi-Tsong Lin

Abstract:

A vertical SOI-based MOSFET with trench body structure operated as 1T DRAM cell at various temperatures has been studied and investigated. Different operation temperatures are assigned for the device for its performance comparison, thus the thermal stability is carefully evaluated for the future memory device applications. Based on the simulation, the vertical SOI-based MOSFET with trench body structure demonstrates the electrical characteristics properly and possess conspicuous kink effect at various operation temperatures. Transient characteristics were also performed to prove that its programming window values and retention time behaviors are acceptable when the new 1T DRAM cell is operated at high operation temperature.

Keywords: SOI, 1T DRAM, thermal stability.

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Authors: A. Fakhfakh, N. Ksentini, M. Loulou, N. Masmoudi, J. J. Charlot

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Today, design requirements are extending more and more from electronic (analogue and digital) to multidiscipline design. These current needs imply implementation of methodologies to make the CAD product reliable in order to improve time to market, study costs, reusability and reliability of the design process. This paper proposes a high level design approach applied for the characterization and the optimization of Switched-Current Sigma- Delta Modulators. It uses the new hardware description language VHDL-AMS to help the designers to optimize the characteristics of the modulator at a high level with a considerably reduced CPU time before passing to a transistor level characterization.

Keywords: high level design, optimization, switched-Current Sigma-Delta Modulators, VHDL-AMS.

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Authors: Vishnu Pratap Singh Kirar

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Memristor is also known as the fourth fundamental passive circuit element. When current flows in one direction through the device, the electrical resistance increases and when current flows in the opposite direction, the resistance decreases. When the current is stopped, the component retains the last resistance that it had, and when the flow of charge starts again, the resistance of the circuit will be what it was when it was last active. It behaves as a nonlinear resistor with memory. Recently memristors have generated wide research interest and have found many applications. In this paper we survey the various applications of memristors which include non volatile memory, nanoelectronic memories, computer logic, neuromorphic computer architectures low power remote sensing applications, crossbar latches as transistor replacements, analog computations and switches.

Keywords: Memristor, non-volatile memory, arithmatic operation, programmable resistor.

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Authors: K. Karami, S. Hassan, S. Taking, A. Ofiare, A. Dhongde, A. Al-Khalidi, E. Wasige

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We have made a comparative study on the influence of Al2O3 and HfO2 grown using Atomic Layer Deposition (ALD) technique as dielectric in the AlGaN/GaN metal oxide semiconductor high electron mobility transistor (MOS-HEMT) structure. Five samples consisting of 20 nm and 10 nm each of A2lO3 and HfO2 respectively and a Schottky gate HEMT, were fabricated and measured. The threshold voltage shifts towards negative by 0.1 V and 1.8 V for 10 nm thick HfO2 and 10 nm thick Al2O3 gate dielectric layers, respectively. The negative shift for the 20 nm HfO2 and 20 nm Al2O3 were 1.2 V and 4.9 V, respectively. Higher gm/IDS (transconductance to drain current) ratio was also obtained in HfO2 than Al2O3. With both materials as dielectric, a significant reduction in the gate leakage current in the order of 104 was obtained compared to the sample without the dielectric material.

Keywords: AlGaN/GaN HEMTs, Al2O3, HfO2, MOSHEMTs.

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Authors: Paulo Gomes, Adelaide Figueiredo

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We consider n individuals described by p standardized variables, represented by points of the surface of the unit hypersphere S_n-1. For a previous choice of n individuals we suppose that the set of observables variables comes from a mixture of bipolar Watson distribution defined on the hypersphere. EM and Dynamic Clusters algorithms are used for identification of such mixture. We obtain estimates of parameters for each Watson component and then a partition of the set of variables into homogeneous groups of variables. Additionally we will present a factor analysis model where unobservable factors are just the maximum likelihood estimators of Watson directional parameters, exactly the first principal component of data matrix associated to each group previously identified. Such alternative model it will yield us to directly interpretable solutions (simple structure), avoiding factors rotations.

Keywords: Dynamic Clusters algorithm, EM algorithm, Factor analysis model, Hierarchical Clustering, Watson distribution.

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Authors: G. Bal, D. Uygun

Abstract:

This paper describes the design and modeling procedure of a novel 5-phase segment type switched reluctance motor (ST-SRM) under simultaneous two-phase (bipolar) excitation of windings. The rotor cores of ST-SRM are embedded in an aluminum block as well as to improve the performance characteristics. The magnetic circuit of the produced ST-SRM is constructed so that the magnetic flux paths are short and exclusive to each phase, thereby minimizing the commutation switching and eddy current losses in the laminations. The design and simulation principles presented apply primarily to conventional SRM and ST-SRM. It is proved that the novel 5-phase switched reluctance motor under two-phase excitation is superior among the criteria used in comparison. The purposed model is particularly well suited for high torque and weight constrained applications such as automobiles, aerospace and military applications.

Keywords: Segmental Rotor Pairs, Two-phase Excitation, Commutation Switching, Aluminum Block.

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Authors: Nasser Erfani Majd, Mojtaba Lotfizad

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In this paper, an ultra low power and low jitter 12bit CMOS digitally controlled oscillator (DCO) design is presented. Based on a ring oscillator implemented with low power Schmitt trigger based inverters. Simulation of the proposed DCO using 32nm CMOS Predictive Transistor Model (PTM) achieves controllable frequency range of 550MHz~830MHz with a wide linearity and high resolution. Monte Carlo simulation demonstrates that the time-period jitter due to random power supply fluctuation is under 31ps and the power consumption is 0.5677mW at 750MHz with 1.2V power supply and 0.53-ps resolution. The proposed DCO has a good robustness to voltage and temperature variations and better linearity comparing to the conventional design.

Keywords: digitally controlled oscillator (DCO), low power, jitter; good linearity, robust

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Authors: Soo-Yeon Lee, Seung-Min Song, Moon-Kyu Song, Woo-Geun Lee, Kap-Soo Yoon, Jang-Yeon Kwon, Min-Koo Han

Abstract:

We fabricated the inverted-staggered etch stopper structure oxide-based TFT and investigated the characteristics of oxide TFT under the 400 nm wavelength light illumination. When 400 nm light was illuminated, the threshold voltage (Vth) decreased and subthreshold slope (SS) increased at forward sweep, while Vth and SS were not altered when larger wavelength lights, such as 650 nm, 550 nm and 450 nm, were illuminated. At reverse sweep, the transfer curve barely changed even under 400 nm light. Our experimental results support that photo-induced hole carriers are captured by donor-like interface trap and it caused the decrease of Vth and increase of SS. We investigated the interface trap density increases proportionally to the photo-induced hole concentration at active layer.

Keywords: thin film transistor, oxide-based semiconductor, lightresponse

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Authors: Abdalla Mohamed Eblabla

Abstract:

Due to the high increase in and demand for a wide assortment of applications that require low-cost, high-efficiency, and compact systems, RF power amplifiers are considered the most critical design blocks and power consuming components in wireless communication, TV transmission, radar, and RF heating. Therefore, much research has been carried out in order to improve the performance of power amplifiers. Classes-A, B, C, D, E and F are the main techniques for realizing power amplifiers.

An implementation of high efficiency class-F power amplifier with Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) was realized in this paper. The simulation and optimization of the class-F power amplifier circuit model was undertaken using Agilent’s Advanced Design system (ADS). The circuit was designed using lumped elements.

Keywords: Power Amplifier (PA), Gallium Nitride (GaN), Agilent’s Advanced Design system (ADS) and lumped elements.

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Authors: Dawit Burusie Abdi, Mamidala Jagadesh Kumar

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In this paper, using 2D TCAD simulations, the application of a dual material gate (DMG) for suppressing ambipolar conduction in a tunnel field effect transistor (TFET) is demonstrated. Using the proposed DMG concept, the ambipolar conduction can be effectively suppressed even if the drain doping is as high as that of the source doping. Achieving this symmetrical doping, without the ambipolar conduction in TFETs, gives the advantage of realizing both n-type and p-type devices with the same doping sequences. Furthermore, the output characteristics of the DMG TFET exhibit a good saturation when compared to that of the gate-drain underlap approach. This improved behavior of the DMG TFET makes it a good candidate for inverter based logic circuits.

Keywords: Dual material gate, suppressing ambipolar current, symmetrically doped TFET, tunnel FETs, PNPN TFET.

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Authors: C. M. M. Paschoal, M. L. Sobrinho, D. do N. Souza, J. Antônio Filho, L. A. P. Santos

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Computed tomography (CT) dosimetry normally uses an ionization chamber 100 mm long to estimate the computed tomography dose index (CTDI), however some reports have already indicated that small devices could replace the long ion chamber to improve quality assurance procedures in CT dosimetry. This paper presents a novel dosimetry system based in a commercial phototransistor evaluated for CT dosimetry. Three detector configurations were developed for this system: with a single, two and four devices. Dose profile measurements were obtained with them and their angular response were evaluated. The results showed that the novel dosimetry system with the phototransistor could be an alternative for CT dosimetry. It allows to obtain the CT dose profile in details and also to estimate the CTDI in longer length than the 100 mm pencil chamber. The angular response showed that the one device detector configuration is the most adequate among the three configurations analyzed in this study.

Keywords: Computed tomography, dosimetry, photo-transistor

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