@article{(Open Science Index):https://publications.waset.org/pdf/13048,
	  title     = {Hardware Description Language Design of Σ-Δ Fractional-N Phase-Locked Loop for Wireless Applications},
	  author    = {Ahmed El Oualkadi and  Abdellah Ait Ouahman},
	  country	= {},
	  institution	= {},
	  abstract     = {This paper discusses a systematic design of a Σ-Δ fractional-N Phase-Locked Loop based on HDL behavioral modeling. The proposed design consists in describing the mixed behavior of this PLL architecture starting from the specifications of each building block. The HDL models of critical PLL blocks have been described in VHDL-AMS to predict the different specifications of the PLL. The effect of different noise sources has been efficiently introduced to study the PLL system performances. The obtained results are compared with transistor-level simulations to validate the effectiveness of the proposed models for wireless applications in the frequency range around 2.45 GHz.
},
	    journal   = {International Journal of Electronics and Communication Engineering},
	  volume    = {3},
	  number    = {4},
	  year      = {2009},
	  pages     = {978 - 985},
	  ee        = {https://publications.waset.org/pdf/13048},
	  url   	= {https://publications.waset.org/vol/28},
	  bibsource = {https://publications.waset.org/},
	  issn  	= {eISSN: 1307-6892},
	  publisher = {World Academy of Science, Engineering and Technology},
	  index 	= {Open Science Index 28, 2009},
	}