Hardware Description Language Design of Σ-Δ Fractional-N Phase-Locked Loop for Wireless Applications
This paper discusses a systematic design of a Σ-Δ fractional-N Phase-Locked Loop based on HDL behavioral modeling. The proposed design consists in describing the mixed behavior of this PLL architecture starting from the specifications of each building block. The HDL models of critical PLL blocks have been described in VHDL-AMS to predict the different specifications of the PLL. The effect of different noise sources has been efficiently introduced to study the PLL system performances. The obtained results are compared with transistor-level simulations to validate the effectiveness of the proposed models for wireless applications in the frequency range around 2.45 GHz.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1080400Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 3533
 Design Automation Standards Committee of the IEEE Computer Society, IEEE Standard VHDL Analog and Mixed Signal Extensions. - 314 pages, Doc., IEEE Std 1076.1-1999, 18 March 1999.
 Gregory Peterson, Peter J. Ashenden, Darrell A. Teegarden, The System Designer's Guide to VHDL-AMS: Analog, Mixed-Signal, and Mixed- Technology Modeling, Morgan Kaufmann Publishers; 2002.
 Y. Hervé, VHDL-AMS: applications et enjeux industriels, Dunod, Paris 2002.
 T.A. Riley, M. A. Copeland. Delta-Sigma Modulation in Fractional-N Frequency Synthesis. In IEEE J. Solid State Circuits, vol. 28, pp. 553- 559, May 1993.
 M.H. Perrott, T.L. Tewksbury, and C.G. Sodini, A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation. IEEE J. Solid-State Circuits, vol.32, no.12, pp.2048-2060, Dec. 1997.
 M. Hinz, I. Konenkamp and E.H. Horneber. Behavioral Modeling and Simulation of Phase-Locked Loops for RF Front Ends. In IEEE Midwest Symp. On Circuits and Systems, pp. 194-197, Aug. 2000.
 N. Milet-Lewis, G. Monnerie, A. Fakhfakh, and all. A VHDL-AMS library of RF blocks models. IEEE International Workshop on Behavioral Modeling and Simulation, 12 - 14, 2001.
 M.H. Perrott, Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits, Proc. 39th Design Automation Conf., pp.498-503, June 2002.
 M. H. Perrott, M.D. Trott, and C. G. Sodini. A Modeling Approach for Σ-Δ Fractional-N Frequency Synthesizers Allowing Straightforward Noise Analysis. In IEEE Journal of Solid-State Circuits, Vol. 37, No. 8, pp. 1028-1038, Aug. 2002.
 Eldo User-s Manual. Mentor Graphics, 1998.
 K. S. Kundert. Modeling and Simulation of Jitter in Phase-Locked Loops. Cadence Design Systems. San Jose, California, USA.
 A. Mounir, A. Mostafa, and M. Fikry, Automatic behavioural model calibration for efficient PLL system verification. Design, Automation and Test in Europe Conference and Exhibition, pp.280-285, 2003.
 B.A.A. Antao, F.M. El-Turky, and R.H. Leonowich, Behavioral modeling phase-locked loops for mixed-mode simulation. Analog Integr. Circuits Signal Process., vol.10, pp.45-65, 1996.
 T. H. Lee. The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge University Press, pp 455-463, 1998.
 M. Tiebout. Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS. In IEEE J. Solid State Circuits, vol. 36, pp. 1018-1024, July 2001.
 N. M. Filiol, T.A.D. Riley, C. Plett, and M.A. Copeland. An agile ISM band frequency synthesizer with built-in GMSK data modulation. In IEEE Journal od Solide-State Circuits, Vol. 33, No. 7, pp. 998-1008, July 1998.
 K. Kundert. Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers.www.desingers-guide.com, May 2003.
 L. Yang, C. Wakayama and C. Richard Shi. Noise Aware Behavioral Modeling of the S-D Fractional-N Frequency Synthesizer. Proc. Great Lakes Symp. on VLSI, pp. 138-142, 2005.