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Design of Novel SCR-based ESD Protection Device for I/O Clamp in BCD Process

Authors: Yong-Seo Koo, Jin-Woo Jung, Byung-Seok Lee, Dong-Su Kim, Yil-Suk Yang


In this paper, a novel LVTSCR-based device for electrostatic discharge (ESD) protection of integrated circuits (ICs) is designed, fabricated and characterized. The proposed device is similar to the conventional LVTSCR but it has an embedded PMOSFET in the anode n-well to enhance the turn on speed, the clamping capability and the robustness. This is possible because the embedded PMOSFET provides the sub-path of ESD discharge current. The TLP, HBM and MM testing are carried out to verify the ESD performance of the proposed devices, which are fabricated in 0.35um (Bipolar-CMOS-DMOS) BCDMOS process. The device has the robustness of 70mA/um that is higher about 60mA/um than the LVTSCR, approximately.

Keywords: ESD Protection, grounded gate NMOS (GGNMOS), low trigger voltage SCR (LVTSCR)

Digital Object Identifier (DOI):

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[1] S. Dabral and T. Maloney, Basic ESD and I/O Design, New York: Wiley,. 1998.
[2] A. Amerasekera and C. Duvvury ESD in silicon integrated circuits, Wiley, New York 1995.
[3] Chun-Hsiang Lai, Meng-Hwang Liu, Shin Su, Tao-Cheng Lu, and Sam Pan, "A Novel Gate-Coupled SCR ESD Protection Structure With High Latch up Immunity for High-Speed I/O Pad", IEEE Electron Device Letters, vol. 25, pp. 328-330, MAY 2004.
[4] Ming-Dou Ker and Zi-Ping Chen, "SCR Device With Dynamic Holding Voltage for On-Chip ESD Protection in a 0.25-um Fully Salicided CMOS Process", IEEE Trans. Electron Devices, 2004, pp. 1731-1734.
[5] Won Jongil, et al, "The Novel SCR-Based ESD Protection Device with High Holding Voltage", in IEEE International Symposium, pp 1779 - 1782, 2008.
[6] Evan Ground and Marcos Hernandez, "Obtaining TLP-like information from an HBM simulator," EOS/ESD Symp., 2007, pp 2A.3-1-2A.3-7.
[7] W. Stadler, X. Guggenmos, P. Egger H. Gieser and C Musshoff, "Does the TLP Failure Current obtained by Transmission Line Pulsing always correlate to Human body model tests", Proc. EOS/ESD Symp, 1997, pp. 336-372.
[8] G. Notemans, P. de Jong and F. Kuper, Pitfalls, "when correlating TLP, HBM and MM testing", Proc. EOS/ESD Symp, 1998, pp. 170-176.