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Thermal Stability of a Vertical SOI-Based Capacitorless One-Transistor DRAM with Trench-Body Structure
Abstract:A vertical SOI-based MOSFET with trench body structure operated as 1T DRAM cell at various temperatures has been studied and investigated. Different operation temperatures are assigned for the device for its performance comparison, thus the thermal stability is carefully evaluated for the future memory device applications. Based on the simulation, the vertical SOI-based MOSFET with trench body structure demonstrates the electrical characteristics properly and possess conspicuous kink effect at various operation temperatures. Transient characteristics were also performed to prove that its programming window values and retention time behaviors are acceptable when the new 1T DRAM cell is operated at high operation temperature.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1085718Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1274
 H. -J. Wan and C. Hu, "A Capacitorless DRAM cell on SOI substrate" in IEDM Tech. Dig., 1993, pp. 635-638.
 T. Tanaka, E. Yoshida, and T. Miyashita, "Scalability study on a capacitorless 1T-DRAM: from single-gate PD-SOI to double-gate FinDRAM," in IEDM Tech. Dig., 2004, pp. 919-922.
 T. Shino, T. Ohsawa, T. Higashi, K. Fujita, N. Kusunoki, Y. Minami, M. Morikado, H. Nakajima, K. Inoh, T. Hamamoto, and A. Nitayama, "Operation voltage dependence of memory cell characteristics in fully depleted floating-body cell," IEEE Trans. Electron Devices, vol. 52, no. 10, pp. 2220-2226, Oct. 2005.
 S.-W. Ryu, J.-W. Han, C.-J. Kim, and Y.-K. Choi, "Investigation of isolation-dielectric effects of PDSOI FinFET on capacitorless 1TDRAM," IEEE Trans. Electron Devices, vol. 56, no. 12, pp. 3232-3235, Dec. 2009.
 M. G. Ertosun, H. Cho, P. Kapur, and K. C. Saraswa, "A Nanoscale Vertical Double-Gate Single-Transistor Capacitorless DRAM," IEEE Electron Device Lett., vol. 29, no. 6, pp. 615-617, May 2008.
 S. Eminente, S. Cristoloveanu, R. Clerc, A. Ohata, and G. Ghibaubo, "Ultra-thin fully-depleted SOI MOSFETs: special charge properties and coupling effects," Solid State Electron., vol. 51, no. 2, pp. 239-244, Feb. 2007.
 U. Avci, I. Ban, D. Kenche, and P. Chang, "Floating body cell (FBC) memory for 16-nm technology with low variation on thin silicon and 10- nm BOX," in Proc. IEEE Int. SOI Conf., Oct. 2008, pp. 29-30.
 A. Hubert, M. Bawedin, S. Cristoloveanu, and T. Ernst, "Dimensional effects and scalability of the Meta-Stable Dip (MSD) memory effect for 1T-DRAM SOI MOSFETs," Solid State Electron., vol. 53, no. 12, pp. 1280-1286, Dec. 2009.C. J. Kaufman, Rocky Mountain Research Lab., Boulder, CO, private communication, May 1995.
 N. Rodriguez, F. Gamiz, and S. Cristoloveanu, "A-RAM Memory Cell: Concept and Operation," IEEE Electron Device Lett., vol. 31, no. 9, pp. 972-974, Sept.. 2010. M. Young, The Techincal Writers Handbook. Mill Valley, CA: University Science, 1989.
 J.-T. Lin, K.-D. Huang, and B.-T. Jheng, "Performances of a capacitorless 1T-DRAM using polycrystalline silicon thin-film transistors with trenched body," IEEE Electron Device Lett., vol. 29, no. 11, pp. 1222-1225, Nov. 2008.
 J.-T. Lin, T.-F. Chang, Y.-C. Eng, P.-H. Lin, and C.-H. Chen, "Characteristics of a Smiling Polysilicon Thin-Film Transistor" IEEE Electron Device Lett., vol. 33, no. 6, pp. 830-832, Jun. 2012.
 J.-T. Lin, P.-H. Lin, Y.-C. Eng, and Y.-R. Chen, "A Novel Vertical SOIBased 1T-DRAM with Trench-Body Structure," IEEE Trans. Electron Devices, in press.
 User`s manual, ISE-TCAD, 2004.