Search results for: SNWT (silicon nanowire transistor)
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 303

Search results for: SNWT (silicon nanowire transistor)

153 Size Dependence of 1D Superconductivity in NbN Nanowires on Suspended Carbon Nanotubes

Authors: T. Hashimoto, N. Miki, H. Maki

Abstract:

We report the size dependence of 1D superconductivity in ultrathin (10-130 nm) nanowires produced by coating suspended carbon nanotubes with a superconducting NbN thin film. The resistance-temperature characteristic curves for samples with ≧25 nm wire width show the superconducting transition. On the other hand, for the samples with 10-nm width, the superconducting transition is not exhibited owing to the quantum size effect. The differential resistance vs. current density characteristic curves show some peak, indicating that Josephson junctions are formed in nanowires. The presence of the Josephson junctions is well explained by the measurement of the magnetic field dependence of the critical current. These understanding allow for the further expansion of the potential application of NbN, which is utilized for single photon detectors and so on.

Keywords: NbN nanowire, carbon nanotube, quantum size effect, Josephson junction

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152 Optimum Surface Roughness Prediction in Face Milling of High Silicon Stainless Steel

Authors: M. Farahnakian, M.R. Razfar, S. Elhami-Joosheghan

Abstract:

This paper presents an approach for the determination of the optimal cutting parameters (spindle speed, feed rate, depth of cut and engagement) leading to minimum surface roughness in face milling of high silicon stainless steel by coupling neural network (NN) and Electromagnetism-like Algorithm (EM). In this regard, the advantages of statistical experimental design technique, experimental measurements, artificial neural network, and Electromagnetism-like optimization method are exploited in an integrated manner. To this end, numerous experiments on this stainless steel were conducted to obtain surface roughness values. A predictive model for surface roughness is created by using a back propogation neural network, then the optimization problem was solved by using EM optimization. Additional experiments were performed to validate optimum surface roughness value predicted by EM algorithm. It is clearly seen that a good agreement is observed between the predicted values by EM coupled with feed forward neural network and experimental measurements. The obtained results show that the EM algorithm coupled with back propogation neural network is an efficient and accurate method in approaching the global minimum of surface roughness in face milling.

Keywords: cutting parameters, face milling, surface roughness, artificial neural network, Electromagnetism-like algorithm,

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151 Design of Low Noise Amplifiers for 10 GHz Application

Authors: Makesh Iyer, T. Shanmuganantham

Abstract:

This work deals with the designing of an efficient low noise amplifier for 10.00 GHz applications. The amplifier is designed using Gallium Arsenide High Electron Mobility Transistor (GaAs HEMT) ATF – 36077 with inductive source degeneration technique which is one of the techniques to improve the stability of the potentially unstable device and make it unconditionally stable. Also, different substrates are used for designing the LNA to identify the suitable substrate that gives optimum results. It is observed that the noise immunity is more in Low Noise Amplifier (LNA) designed using RT Duroid 5880 substrate. This design resulted in noise figure of 0.859 dB and power gain of 15.530 dB. The comparative analysis of the LNA design is discussed in this paper.

Keywords: Low noise amplifier, substrate, distributed components, gain, noise figure.

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150 Perturbation Based Modelling of Differential Amplifier Circuit

Authors: Rahul Bansal, Sudipta Majumdar

Abstract:

This paper presents the closed form nonlinear expressions of bipolar junction transistor (BJT) differential amplifier (DA) using perturbation method. Circuit equations have been derived using Kirchhoff’s voltage law (KVL) and Kirchhoff’s current law (KCL). The perturbation method has been applied to state variables for obtaining the linear and nonlinear terms. The implementation of the proposed method is simple. The closed form nonlinear expressions provide better insights of physical systems. The derived equations can be used for signal processing applications.

Keywords: Differential amplifier, perturbation method, Taylor series.

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149 Fractional-Order Modeling of GaN High Electron Mobility Transistors for Switching Applications

Authors: Anwar H. Jarndal, Ahmed S. Elwakil

Abstract:

In this paper, a fraction-order model for pad parasitic effect of GaN HEMT on Si substrate is developed and validated. Open de-embedding structure is used to characterize and de-embed substrate loading parasitic effects. Unbiased device measurements are implemented to extract parasitic inductances and resistances. The model shows very good simulation for S-parameter measurements under different bias conditions. It has been found that this approach can improve the simulation of intrinsic part of the transistor, which is very important for small- and large-signal modeling process.

Keywords: Fractional-order modeling, GaN HEMT, Si-substrate, open de-embedding structure.

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148 Effect of Field Dielectric Material on Performance of InGaAs Power LDMOSFET

Authors: Yashvir Singh, Swati Chamoli

Abstract:

In this paper, a power laterally-diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) on In0.53Ga0.47As is presented. The device utilizes a thicker field-oxide with low dielectric constant under the field-plate in order to achieve possible reduction in device capacitances and reduced-surface-field effect. Using 2D numerical simulations, performance of the proposed device is analyzed and compared with that of the conventional LDMOSFET. The proposed structure provides 50% increase in the breakdown voltage, 21% increase in transit frequency, and 72% improvement in figure-of-merit over the conventional device for same cell pitch.

Keywords: InGaAs, dielectric, lateral, power MOSFET.

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147 Graphene/h-BN Heterostructure Interconnects

Authors: Nikhil Jain, Yang Xu, Bin Yu

Abstract:

The material behavior of graphene, a single layer of carbon lattice, is extremely sensitive to its dielectric environment. We demonstrate improvement in electronic performance of graphene nanowire interconnects with full encapsulation by lattice-matching, chemically inert, 2D layered insulator hexagonal boron nitride (h- BN). A novel layer-based transfer technique is developed to construct the h-BN/MLG/h-BN heterostructures. The encapsulated graphene wires are characterized and compared with that on SiO2 or h-BN substrate without passivating h-BN layer. Significant improvements in maximum current-carrying density, breakdown threshold, and power density in encapsulated graphene wires are observed. These critical improvements are achieved without compromising the carrier transport characteristics in graphene. Furthermore, graphene wires exhibit electrical behavior less insensitive to ambient conditions, as compared with the non-passivated ones. Overall, h-BN/graphene/h- BN heterostructure presents a robust material platform towards the implementation of high-speed carbon-based interconnects.

Keywords: Two-dimensional nanosheet, graphene, hexagonal boron nitride, heterostructure, interconnects.

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146 Hardware Description Language Design of Σ-Δ Fractional-N Phase-Locked Loop for Wireless Applications

Authors: Ahmed El Oualkadi, Abdellah Ait Ouahman

Abstract:

This paper discusses a systematic design of a Σ-Δ fractional-N Phase-Locked Loop based on HDL behavioral modeling. The proposed design consists in describing the mixed behavior of this PLL architecture starting from the specifications of each building block. The HDL models of critical PLL blocks have been described in VHDL-AMS to predict the different specifications of the PLL. The effect of different noise sources has been efficiently introduced to study the PLL system performances. The obtained results are compared with transistor-level simulations to validate the effectiveness of the proposed models for wireless applications in the frequency range around 2.45 GHz.

Keywords: Phase-locked loop, frequency synthesizer, fractional-N PLL, Σ-Δ modulator, HDL models

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145 Hybrid Recovery of Copper and Silver from PV Ribbon and Ag Finger of EOL Solar Panels

Authors: T. Patcharawit, C. Kansomket, N. Wongnaree, W. Kritsrikan, T. Yingnakorn, S. Khumkoa

Abstract:

Recovery of pure copper and silver from end-of-life photovoltaic (PV) panels was investigated in this paper using an effective hybrid pyro-hydrometallurgical process. In the first step of waste treatment, solar panel waste was first dismantled to obtain a PV sheet to be cut and calcined at 500 °C, to separate out PV ribbon from glass cullet, ash, and volatile while the silicon wafer containing silver finger was collected for recovery. In the second step of metal recovery, copper recovery from PV ribbon was via 1-3 M HCl leaching with SnCl₂ and H₂O₂ additions in order to remove the tin-lead coating on the ribbon. The leached copper band was cleaned and subsequently melted as an anode for the next step of electrorefining. Stainless steel was set as the cathode with CuSO₄ as an electrolyte, and at a potential of 0.2 V, high purity copper of 99.93% was obtained at 96.11% recovery after 24 hours. For silver recovery, the silicon wafer containing silver finger was leached using HNO₃ at 1-4 M in an ultrasonic bath. In the next step of precipitation, silver chloride was then obtained and subsequently reduced by sucrose and NaOH to give silver powder prior to oxy-acetylene melting to finally obtain pure silver metal. The integrated recycling process is considered to be economical, providing effective recovery of high purity metals such as copper and silver while other materials such as aluminum, copper wire, glass cullet can also be recovered to be reused commercially. Compounds such as PbCl₂ and SnO₂ obtained can also be recovered to enter the market.

Keywords: Electrorefining, leaching, calcination, PV ribbon, silver finger, solar panel.

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144 Development of Nondestructive Imaging Analysis Method Using Muonic X-Ray with a Double-Sided Silicon Strip Detector

Authors: I-Huan Chiu, Kazuhiko Ninomiya, Shin’ichiro Takeda, Meito Kajino, Miho Katsuragawa, Shunsaku Nagasawa, Atsushi Shinohara, Tadayuki Takahashi, Ryota Tomaru, Shin Watanabe, Goro Yabu

Abstract:

In recent years, a nondestructive elemental analysis method based on muonic X-ray measurements has been developed and applied for various samples. Muonic X-rays are emitted after the formation of a muonic atom, which occurs when a negatively charged muon is captured in a muon atomic orbit around the nucleus. Because muonic X-rays have a higher energy than electronic X-rays due to the muon mass, they can be measured without being absorbed by a material. Thus, estimating the two-dimensional (2D) elemental distribution of a sample became possible using an X-ray imaging detector. In this work, we report a non-destructive imaging experiment using muonic X-rays at Japan Proton Accelerator Research Complex. The irradiated target consisted of a polypropylene material, and a double-sided silicon strip detector, which was developed as an imaging detector for astronomical obervation, was employed. A peak corresponding to muonic X-rays from the carbon atoms in the target was clearly observed in the energy spectrum at an energy of 14 keV, and 2D visualizations were successfully reconstructed to reveal the projection image from the target. This result demonstrates the potential of the nondestructive elemental imaging method that is based on muonic X-ray measurement. To obtain a higher position resolution for imaging a smaller target, a new detector system will be developed to improve the statistical analysis in further research.

Keywords: DSSD, muon, muonic X-ray, imaging, non-destructive analysis

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143 Bias Stability of a-IGZO TFT and a new Shift-Register Design Suitable for a-IGZO TFT

Authors: Young Wook Lee, Sun-Jae Kim, Soo-Yeon Lee, Moon-Kyu Song, Woo-Geun Lee Min-Koo Han

Abstract:

We have fabricated a-IGZO TFT and investigated the stability under positive DC and AC bias stress. The threshold voltage of a-IGZO TFT shifts positively under those biases, and that reduces on-current. For this reason, conventional shift-register circuit employing TFTs which stressed by positive bias will be unstable, may do not work properly. We have designed a new 6-transistor shift-register, which has less transistors than prior circuits. The TFTs of the proposed shift-register are not suffering from positive DC or AC stress, mainly kept unbiased. Despite the compact design, the stable output signal was verified through the SPICE simulation even under RC delay of clock signal.

Keywords: Indium Gallium Zinc Oxide (IGZO), Thin FilmTransistor (TFT), shift-register

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142 Geometric Modeling of Illumination on the TFT-LCD Panel using Bezier Surface

Authors: Kyong-min Lee, Moon Soo Chang, PooGyeon Park

Abstract:

In this paper, we propose a geometric modeling of illumination on the patterned image containing etching transistor. This image is captured by a commercial camera during the inspection of a TFT-LCD panel. Inspection of defect is an important process in the production of LCD panel, but the regional difference in brightness, which has a negative effect on the inspection, is due to the uneven illumination environment. In order to solve this problem, we present a geometric modeling of illumination consisting of an interpolation using the least squares method and 3D modeling using bezier surface. Our computational time, by using the sampling method, is shorter than the previous methods. Moreover, it can be further used to correct brightness in every patterned image.

Keywords: Bezier, defect, geometric modeling, illumination, inspection, LCD, panel.

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141 LFSR Counter Implementation in CMOS VLSI

Authors: Doshi N. A., Dhobale S. B., Kakade S. R.

Abstract:

As chip manufacturing technology is suddenly on the threshold of major evaluation, which shrinks chip in size and performance, LFSR (Linear Feedback Shift Register) is implemented in layout level which develops the low power consumption chip, using recent CMOS, sub-micrometer layout tools. Thus LFSR counter can be a new trend setter in cryptography and is also beneficial as compared to GRAY & BINARY counter and variety of other applications. This paper compares 3 architectures in terms of the hardware implementation, CMOS layout and power consumption, using Microwind CMOS layout tool. Thus it provides solution to a low power architecture implementation of LFSR in CMOS VLSI.

Keywords: Chip technology, Layout level, LFSR, Pass transistor

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140 Design and Realization of an Electronic Load for a PEM Fuel Cell

Authors: Arafet Bouaicha, Hatem Allegui, Amar Rouane, El-Hassane Aglzim, Abdelkader Mami

Abstract:

In order to further understand the behavior of PEM fuel cell and optimize their performance, it is necessary to perform measurements in real time. The internal impedance measurement by electrochemical impedance spectroscopy (EIS) is of great importance. In this work, we present the impedance measurement method of a PEM fuel cell by electrochemical impedance spectroscopy method and the realization steps of electronic load for this measuring technique implementation. The theoretical results are obtained from the simulation of software PSPICE® and experimental tests are carried out using the Ballard Nexa™ PEM fuel cell system.

Keywords: Electronic load, MOS transistor, PEM fuel cell, Impedance measurement, Electrochemical Impedance Spectroscopy (EIS).

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139 Channel Length Modulation Effect on Monolayer Graphene Nanoribbon Field Effect Transistor

Authors: Mehdi Saeidmanesh, Razali Ismail

Abstract:

Recently, Graphene Nanoribbon Field Effect Transistors (GNR FETs) attract a great deal of attention due to their better performance in comparison with conventional devices. In this paper, channel length Modulation (CLM) effect on the electrical characteristics of GNR FETs is analytically studied and modeled. To this end, the special distribution of the electric potential along the channel and current-voltage characteristic of the device is modeled. The obtained results of analytical model are compared to the experimental data of published works. As a result, it is observable that considering the effect of CLM, the current-voltage response of GNR FET is more realistic.

Keywords: Graphene nanoribbon, field effect transistors, short channel effects, channel length modulation.

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138 Parameters Extraction for Pseudomorphic HEMTs Using Genetic Algorithms

Authors: Mazhar B. Tayel, Amr H. Yassin

Abstract:

A proposed small-signal model parameters for a pseudomorphic high electron mobility transistor (PHEMT) is presented. Both extrinsic and intrinsic circuit elements of a smallsignal model are determined using genetic algorithm (GA) as a stochastic global search and optimization tool. The parameters extraction of the small-signal model is performed on 200-μm gate width AlGaAs/InGaAs PHEMT. The equivalent circuit elements for a proposed 18 elements model are determined directly from the measured S- parameters. The GA is used to extract the parameters of the proposed small-signal model from 0.5 up to 18 GHz.

Keywords: PHEMT, Genetic Algorithms, small signal modeling, optimization.

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137 Creation of GaxCo1-xZnSe0.4 (x = 0.1, 0.3, 0.5) Nanoparticles Using Pulse Laser Ablation Method

Authors: Yong Pan, Li Wang, Xue Qiong Su, Dong Wen Gao

Abstract:

To date, nanomaterials have received extensive attention over the years because of their wide application. Various nanomaterials such as nanoparticles, nanowire, nanoring, nanostars and other nanostructures have begun to be systematically studied. The preparation of these materials by chemical methods is not only costly, but also has a long cycle and high toxicity. At the same time, preparation of nanoparticles of multi-doped composites has been limited due to the special structure of the materials. In order to prepare multi-doped composites with the same structure as macro-materials and simplify the preparation method, the GaxCo1-xZnSe0.4 (x = 0.1, 0.3, 0.5) nanoparticles are prepared by Pulse Laser Ablation (PLA) method. The particle component and structure are systematically investigated by X-ray diffraction (XRD) and Raman spectra, which show that the success of our preparation and the same concentration between nanoparticles (NPs) and target. Morphology of the NPs characterized by Transmission Electron Microscopy (TEM) indicates the circular-shaped particles in preparation. Fluorescence properties are reflected by PL spectra, which demonstrate the best performance in concentration of Ga0.3Co0.3ZnSe0.4. Therefore, all the results suggest that PLA is promising to prepare the multi-NPs since it can modulate performance of NPs.

Keywords: PLA, physics, nanoparticles, multi-doped.

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136 Mechanical Properties of 3D Noninterlaced Cf/SiC Composites Prepared through Hybrid Process (CVI+PIP)

Authors: A. Udayakumar, M. Rizvan Basha, M. Stalin, V.V Bhanu Prasad

Abstract:

Three dimensional non-Interlaced carbon fibre reinforced silicon carbide (3-D-Cf/SiC) composites with pyrocarbon interphase were fabricated using isothermal chemical vapor infiltration (ICVI) combined with polymer impregnation pyrolysis (PIP) process. Polysilazane (PSZ) is used as a preceramic polymer to obtain silicon carbide matrix. Thermo gravimetric analysis (TGA), Infrared spectroscopic analysis (IR) and X-ray diffraction (XRD) analysis were carried out on PSZ pyrolysed at different temperatures to understand the pyrolysis and obtaining the optimum pyrolysing condition to yield β-SiC phase. The density of the composites was 1.94 g cm-3 after the 3-D carbon preform was SiC infiltrated for 280 h with one intermediate polysilazane pre-ceramic PIP process. Mechanical properties of the composite materials were investigated under tensile, flexural, shear and impact loading. The values of tensile strength were 200 MPa at room temperature (RT) and 195 MPa at 500°C in air. The average RT flexural strength was 243 MPa. The lower flexural strength of these composites is because of the porosity. The fracture toughness obtained from single edge notched beam (SENB) technique was 39 MPa.m1/2. The work of fracture obtained from the load-displacement curve of SENB test was 22.8 kJ.m-2. The composites exhibited excellent impact resistance and the dynamic fracture toughness of 44.8 kJ.m-2 is achieved as determined from instrumented Charpy impact test. The shear strength of the composite was 93 MPa, which is significantly higher compared 2-D Cf/SiC composites. Microstructure evaluation of fracture surfaces revealed the signatures of fracture processes and showed good support for the higher toughness obtained.

Keywords: 3-D-Cf/SiC, charpy impact test, composites, dynamic fracture toughness, polysilazane, pyrocarbon, Interphase.

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135 Optimization and Determination of Process Parameters in Thin Film SOI Photo-BJMOSFET

Authors: Hai-Qing Xie, Yun Zeng, Yong-Hong Yan, Guo-Liang Zhang, Tai-Hong Wang

Abstract:

We propose photo-BJMOSFET (Bipolar Junction Metal-Oxide-Semiconductor Field Effect Transistor) fabricated on SOI film. ITO film is adopted in the device as gate electrode to reduce light absorption. I-V characteristics of photo-BJMOSFET obtained in dark (dark current) and under 570nm illumination (photo current) are studied furthermore to achieve high photo-to-dark-current contrast ratio. Two variables in the calculation were the channel length and the thickness of the film which were set equal to six different values, i.e., L=2, 4, 6, 8, 10, and 12μm and three different values, i.e., dsi =100, 200 and 300nm, respectively. The results indicate that the greatest photo-to-dark-current contrast ratio is achieved with L=10μm and dsi=200 nm at VGK=0.6V.

Keywords: Photo-to-dark-current contrast ratio, Photo-current, Dark-current, Process parameter

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134 Design of Folded Cascode OTA in Different Regions of Operation through gm/ID Methodology

Authors: H. Daoud Dammak, S. Bensalem, S. Zouari, M. Loulou

Abstract:

This paper presents an optimized methodology to folded cascode operational transconductance amplifier (OTA) design. The design is done in different regions of operation, weak inversion, strong inversion and moderate inversion using the gm/ID methodology in order to optimize MOS transistor sizing. Using 0.35μm CMOS process, the designed folded cascode OTA achieves a DC gain of 77.5dB and a unity-gain frequency of 430MHz in strong inversion mode. In moderate inversion mode, it has a 92dB DC gain and provides a gain bandwidth product of around 69MHz. The OTA circuit has a DC gain of 75.5dB and unity-gain frequency limited to 19.14MHZ in weak inversion region.

Keywords: CMOS IC design, Folded Cascode OTA, gm/ID methodology, optimization.

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133 Thermal Stability of a Vertical SOI-Based Capacitorless One-Transistor DRAM with Trench-Body Structure

Authors: Po-Hsieh Lin, Jyi-Tsong Lin

Abstract:

A vertical SOI-based MOSFET with trench body structure operated as 1T DRAM cell at various temperatures has been studied and investigated. Different operation temperatures are assigned for the device for its performance comparison, thus the thermal stability is carefully evaluated for the future memory device applications. Based on the simulation, the vertical SOI-based MOSFET with trench body structure demonstrates the electrical characteristics properly and possess conspicuous kink effect at various operation temperatures. Transient characteristics were also performed to prove that its programming window values and retention time behaviors are acceptable when the new 1T DRAM cell is operated at high operation temperature.

Keywords: SOI, 1T DRAM, thermal stability.

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132 High Level Characterization and Optimization of Switched-Current Sigma-Delta Modulators with VHDL-AMS

Authors: A. Fakhfakh, N. Ksentini, M. Loulou, N. Masmoudi, J. J. Charlot

Abstract:

Today, design requirements are extending more and more from electronic (analogue and digital) to multidiscipline design. These current needs imply implementation of methodologies to make the CAD product reliable in order to improve time to market, study costs, reusability and reliability of the design process. This paper proposes a high level design approach applied for the characterization and the optimization of Switched-Current Sigma- Delta Modulators. It uses the new hardware description language VHDL-AMS to help the designers to optimize the characteristics of the modulator at a high level with a considerably reduced CPU time before passing to a transistor level characterization.

Keywords: high level design, optimization, switched-Current Sigma-Delta Modulators, VHDL-AMS.

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131 Memristor: The Missing Circuit Element and its Application

Authors: Vishnu Pratap Singh Kirar

Abstract:

Memristor is also known as the fourth fundamental passive circuit element. When current flows in one direction through the device, the electrical resistance increases and when current flows in the opposite direction, the resistance decreases. When the current is stopped, the component retains the last resistance that it had, and when the flow of charge starts again, the resistance of the circuit will be what it was when it was last active. It behaves as a nonlinear resistor with memory. Recently memristors have generated wide research interest and have found many applications. In this paper we survey the various applications of memristors which include non volatile memory, nanoelectronic memories, computer logic, neuromorphic computer architectures low power remote sensing applications, crossbar latches as transistor replacements, analog computations and switches.

Keywords: Memristor, non-volatile memory, arithmatic operation, programmable resistor.

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130 Comparative Study of Al2O3 and HfO2 as Gate Dielectric on AlGaN/GaN MOSHEMTs

Authors: K. Karami, S. Hassan, S. Taking, A. Ofiare, A. Dhongde, A. Al-Khalidi, E. Wasige

Abstract:

We have made a comparative study on the influence of Al2O3 and HfO2 grown using Atomic Layer Deposition (ALD) technique as dielectric in the AlGaN/GaN metal oxide semiconductor high electron mobility transistor (MOS-HEMT) structure. Five samples consisting of 20 nm and 10 nm each of A2lO3 and HfO2 respectively and a Schottky gate HEMT, were fabricated and measured. The threshold voltage shifts towards negative by 0.1 V and 1.8 V for 10 nm thick HfO2 and 10 nm thick Al2O3 gate dielectric layers, respectively. The negative shift for the 20 nm HfO2 and 20 nm Al2O3 were 1.2 V and 4.9 V, respectively. Higher gm/IDS (transconductance to drain current) ratio was also obtained in HfO2 than Al2O3. With both materials as dielectric, a significant reduction in the gate leakage current in the order of 104 was obtained compared to the sample without the dielectric material.

Keywords: AlGaN/GaN HEMTs, Al2O3, HfO2, MOSHEMTs.

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129 A Novel Low Power Digitally Controlled Oscillator with Improved linear Operating Range

Authors: Nasser Erfani Majd, Mojtaba Lotfizad

Abstract:

In this paper, an ultra low power and low jitter 12bit CMOS digitally controlled oscillator (DCO) design is presented. Based on a ring oscillator implemented with low power Schmitt trigger based inverters. Simulation of the proposed DCO using 32nm CMOS Predictive Transistor Model (PTM) achieves controllable frequency range of 550MHz~830MHz with a wide linearity and high resolution. Monte Carlo simulation demonstrates that the time-period jitter due to random power supply fluctuation is under 31ps and the power consumption is 0.5677mW at 750MHz with 1.2V power supply and 0.53-ps resolution. The proposed DCO has a good robustness to voltage and temperature variations and better linearity comparing to the conventional design.

Keywords: digitally controlled oscillator (DCO), low power, jitter; good linearity, robust

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128 Sensitivity of Input Blocking Capacitor on Output Voltage and Current of a PV Inverter Employing IGBTs

Authors: Z.A. Jaffery, Vinay Kumar Chandna, Sunil Kumar Chaudhary

Abstract:

This paper present a MATLAB-SIMULINK model of a single phase 2.5 KVA, 240V RMS controlled PV VSI (Photovoltaic Voltage Source Inverter) inverter using IGBTs (Insulated Gate Bipolar Transistor). The behavior of output voltage, output current, and the total harmonic distortion (THD), with the variation in input dc blocking capacitor (Cdc), for linear and non-linear load has been analyzed. The values of Cdc as suggested by the other authors in their papers are not clearly defined and it poses difficulty in selecting the proper value. As the dc power stored in Cdc, (generally placed parallel with battery) is used as input to the VSI inverter. The simulation results shows the variation in the output voltage and current with different values of Cdc for linear and non-linear load connected at the output side of PV VSI inverter and suggest the selection of suitable value of Cdc.

Keywords: DC Blocking capacitor, IGBTs, PV VSI, THD.

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127 The Light Response Characteristics of Oxide-Based Thin Film Transistors

Authors: Soo-Yeon Lee, Seung-Min Song, Moon-Kyu Song, Woo-Geun Lee, Kap-Soo Yoon, Jang-Yeon Kwon, Min-Koo Han

Abstract:

We fabricated the inverted-staggered etch stopper structure oxide-based TFT and investigated the characteristics of oxide TFT under the 400 nm wavelength light illumination. When 400 nm light was illuminated, the threshold voltage (Vth) decreased and subthreshold slope (SS) increased at forward sweep, while Vth and SS were not altered when larger wavelength lights, such as 650 nm, 550 nm and 450 nm, were illuminated. At reverse sweep, the transfer curve barely changed even under 400 nm light. Our experimental results support that photo-induced hole carriers are captured by donor-like interface trap and it caused the decrease of Vth and increase of SS. We investigated the interface trap density increases proportionally to the photo-induced hole concentration at active layer.

Keywords: thin film transistor, oxide-based semiconductor, lightresponse

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126 High Efficiency Class-F Power Amplifier Design

Authors: Abdalla Mohamed Eblabla

Abstract:

Due to the high increase in and demand for a wide assortment of applications that require low-cost, high-efficiency, and compact systems, RF power amplifiers are considered the most critical design blocks and power consuming components in wireless communication, TV transmission, radar, and RF heating. Therefore, much research has been carried out in order to improve the performance of power amplifiers. Classes-A, B, C, D, E and F are the main techniques for realizing power amplifiers.

An implementation of high efficiency class-F power amplifier with Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) was realized in this paper. The simulation and optimization of the class-F power amplifier circuit model was undertaken using Agilent’s Advanced Design system (ADS). The circuit was designed using lumped elements.

Keywords: Power Amplifier (PA), Gallium Nitride (GaN), Agilent’s Advanced Design system (ADS) and lumped elements.

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125 Suppressing Ambipolar Conduction Using Dual Material Gate in Tunnel-FETs Having Heavily Doped Drain

Authors: Dawit Burusie Abdi, Mamidala Jagadesh Kumar

Abstract:

In this paper, using 2D TCAD simulations, the application of a dual material gate (DMG) for suppressing ambipolar conduction in a tunnel field effect transistor (TFET) is demonstrated. Using the proposed DMG concept, the ambipolar conduction can be effectively suppressed even if the drain doping is as high as that of the source doping. Achieving this symmetrical doping, without the ambipolar conduction in TFETs, gives the advantage of realizing both n-type and p-type devices with the same doping sequences. Furthermore, the output characteristics of the DMG TFET exhibit a good saturation when compared to that of the gate-drain underlap approach. This improved behavior of the DMG TFET makes it a good candidate for inverter based logic circuits.

Keywords: Dual material gate, suppressing ambipolar current, symmetrically doped TFET, tunnel FETs, PNPN TFET.

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124 Nonlinear Thermal Expansion Model for SiC/Al

Authors: T.R. Sahroni, S. Sulaiman, I. Romli, M.R. Salleh, H.A. Ariff

Abstract:

The thermal expansion behaviour of silicon carbide (SCS-2) fibre reinforced 6061 aluminium matrix composite subjected to the influenced thermal mechanical cycling (TMC) process were investigated. The thermal stress has important effect on the longitudinal thermal expansion coefficient of the composites. The present paper used experimental data of the thermal expansion behaviour of a SiC/Al composite for temperatures up to 370°C, in which their data was used for carrying out modelling of theoretical predictions.

Keywords: Nonlinear, thermal, fibre reinforced, metal matrixcomposites

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