%0 Journal Article
	%A M.Hosseinghadiry and  H. Mohammadi and  M.Nadisenejani
	%D 2009
	%J International Journal of Electrical and Computer Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 28, 2009
	%T Two New Low Power High Performance Full Adders with Minimum Gates
	%U https://publications.waset.org/pdf/6897
	%V 28
	%X with increasing circuits- complexity and demand to
use portable devices, power consumption is one of the most
important parameters these days. Full adders are the basic block of
many circuits. Therefore reducing power consumption in full adders
is very important in low power circuits. One of the most powerconsuming
modules in full adders is XOR/XNOR circuit. This paper
presents two new full adders based on two new logic approaches. The
proposed logic approaches use one XOR or XNOR gate to implement
a full adder cell. Therefore, delay and power will be decreased. Using
two new approaches and two XOR and XNOR gates, two new full
adders have been implemented in this paper. Simulations are carried
out by HSPICE in 0.18μm bulk technology with 1.8V supply voltage.
The results show that the ten-transistors proposed full adder has 12%
less power consumption and is 5% faster in comparison to MB12T
full adder. 9T is more efficient in area and is 24% better than similar
10T full adder in term of power consumption. The main drawback of
the proposed circuits is output threshold loss problem.
	%P 1201 - 1208