Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 32131
Two New Low Power High Performance Full Adders with Minimum Gates

Authors: M.Hosseinghadiry, H. Mohammadi, M.Nadisenejani


with increasing circuits- complexity and demand to use portable devices, power consumption is one of the most important parameters these days. Full adders are the basic block of many circuits. Therefore reducing power consumption in full adders is very important in low power circuits. One of the most powerconsuming modules in full adders is XOR/XNOR circuit. This paper presents two new full adders based on two new logic approaches. The proposed logic approaches use one XOR or XNOR gate to implement a full adder cell. Therefore, delay and power will be decreased. Using two new approaches and two XOR and XNOR gates, two new full adders have been implemented in this paper. Simulations are carried out by HSPICE in 0.18μm bulk technology with 1.8V supply voltage. The results show that the ten-transistors proposed full adder has 12% less power consumption and is 5% faster in comparison to MB12T full adder. 9T is more efficient in area and is 24% better than similar 10T full adder in term of power consumption. The main drawback of the proposed circuits is output threshold loss problem.

Keywords: Full adder, XNOR, Low power, High performance, Very Large Scale Integrated Circuit.

Digital Object Identifier (DOI):

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1967


[1] M. W. Elgharbawy, M. A. Bayoumi, "Leakge Sources and Possible Solutions in Nanometer CMOS Technology," IEEE circuit and system magazine, pp. 6-16, 2005.
[2] H. T. Bui, Y. Wang, and Y. Jiang, "Design and Analysis of 10- Transistor Full Adders Using XOR-XNOR Gates," IEEE Trans. Circuits and Syst. II, Analog Digit. Signal Process., vol 49, no. 1, pp. 25-30, Jan. 2002.
[3] A. Kumar, M. A. Bayoumi, "Design of Robust Energy Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style," IEEE Trans. VLSI, vol. 14, no. 12, Dec. 2006.
[4] T. Lynch, E. Swartzlander, "A Spanning Tree Carry Lookahead Adder," IEEE Trans. Comput. vol 41, pp 931-939, Aug. 1992.
[5] R.Shalem, E. John, and L. K. John, "A Novel Low-Power Energy Recovery Full Adder Cell," in proc. of GLSVLSI, pp 380-383, 1999.
[6] K. Navi, M. Maeen, V. Foroutan, S. Timarchi, and O. Kavei, "A Novel Low Power Full-Adder Cell for Low Voltage," Integration the VLSI Journal, 2009.
[7] M. A. Elgamel, S. Goel, and M. a. Bayoumi, "Noise Tolerant Low Voltage XOR-XNOR For Fast Arithmetic," GLSVLSI, 2003.
[8] N. Zhuang, H. Wu, "A New Design of CMOS Full Adder," IEEE Journal of Solid-State Circuits, vol. 27, no. 5, pp. 840-844, May 1992.
[9] N. West, K. Eshraghian, Principles of CMOS VLSI Design, system prospective reading, MA: Addison-Wesley, 1993.
[10] A. M. shams, M. A. Bayoumi, "A Novel High Performance CMOS 1-Bit Full Adder Cell," IEEE Trans. Circuits and Systems II: Analog digital Signal Process. 47 (2000), vol. 47, no. 5, May 2000.
[11] H. T. Bui, Y. Wang, and Y. Jiang, "Design and Analysis of Low Power 10-T Full Adders Using Novel XOR-XNOR Gates," IEEE Trans. On Circuits and Systems II: Analog and Digital signal process. vol. 49, no. 1, Jan. 2002.
[12] S. Goel, A, Kumar, M. A. Bayoumi, "Design of Robust, Energy- Efficient Full Adders for Deep-Submicrometer Design Using Hybrid- CMOS Logic Style," IEEE Trans. on VLSI Systems, vol. 14, no. 12, Dec. 2006.
[13] Y. Jiang, A. Alsheridah, Y. Wang, E. shah, and J. Chung, "A Novel Multiplexer-Based Low Power Full Adder," IEEE Trans. On Circuits and Systems, vol. 51, no. 7, Jul. 2004.
[14] S. Veeramachaneni, M. B. Sirinivas, "New Improved 1-Bit Full Adder Cells," CCECE/CGEI, Canada, 2008.
[15] A. Elgamel, S. Goel, and M. A. Bayoumi, "Noise Tolerant Low Voltage XOR-XNOR for Fast Arithmetic," GLSVLSI, Washington D.C., 2003.