Design and Implementation of 4 Bit Multiplier Using Fault Tolerant Hybrid Full Adder
The fault tolerant system plays a crucial role in the critical applications which are being used in the present scenario. A fault may change the functionality of circuits. Aim of this paper is to design multiplier using fault tolerant hybrid full adder. Fault tolerant hybrid full adder is designed to check and repair any fault in the circuit using self-checking circuit and the self-repairing circuit. Further, the use of conventional logic circuits may result in more area, delay as well as power consumption. In order to reduce these parameters of the circuit, GDI (Gate Diffusion Input) techniques with less number of transistors are used compared to conventional full adder circuit. This reduces the area, delay and power consumption. The proposed method solves the major problems occurring in the most crucial and critical applications.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1314630Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 999
 U. Ko, T. Balsara, and W. Lee, “Low-power design techniques for high-performance CMOS adders”, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 3, no. 2, pp. 327–333, Jun. 1995.
 Abdelmonaem Ayachi, Belgacem Hamdi, “A Fault-Tolerant Full Adder in Double Pass CMOS Transistor”, International Journal of Electrical, Computer, Energetic, Electronic and Communication Engineering, Vol: 10, No: 1, 2016, pp: 36-40.
 Hungse cha, Elizabeth M. Rudnick, Gwan S. choi, Janak H. Patel and Ravishankar K. Iyer “A fast and accurate gate-level transient fault simulation environment”, Proceedings of the International Symposium on Fault-Tolerant Computing, pp. 310-319, June 1993.
 Pankaj Kumar, Rajender Kumar Sharma, “Real-time fault tolerant full adder design for critical applications”, Engineering Science and Technology, an International Journal 19, 2016, pp: 1465–1472.
 Rajkumar Sarma and Veerati Raju, “Design and performance analysis of hybrid adders for high speed arithmetic circuit” International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3, June 2012, pp: 21-32.
 M. Shoba, R. Nakkeeran, “GDI based full adders for energy efficient arithmetic applications”, Eng. Sci. Technol. Int. J. 19 (01), 2016, pp: 485–496
 K. Navi, V. Foroutan, M. RahimiAzghad, M. Maeen, Ebrahimpour, M. Kaveh, O. Kavehei, “A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverter,” Microelectron J. 40 (10), 2009, pp:1441–1448.
 SudeshnaSarkar, Monika Jain, ArpitaSaha, AmitRathi, “Gate Diffusion Input: A technique for fast digital circuits”, IOSR Journal of VLSI and Signal Processing (IOSR-JVSP), Volume 4, Issue 2, Ver. IV, Mar.-Apr. 2014, pp: 49-53.
 Pankaj Kumar, Rajender Kumar Sharma, “Low voltage high performance hybrid full adder”, Engineering Science and Technology, an International Journal 19, 2016, pp: 559–565.
 Sumit Vaidya and Deepak Dandekar, “Delay-Power performance comparison of multipliers in VLSI circuit design”, International Journal of Computer Networks & Communications (IJCNC), Vol.2, No.4, July 2010, pp.47-56.