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High Level Synthesis of Digital Filters Based On Sub-Token Forwarding
Abstract:High level synthesis (HLS) is a process which generates register-transfer level design for digital systems from behavioral description. There are many HLS algorithms and commercial tools. However, most of these algorithms consider a behavioral description for the system when a single token is presented to the system. This approach does not exploit extra hardware efficiently, especially in the design of digital filters where common operations may exist between successive tokens. In this paper, we modify the behavioral description to process multiple tokens in parallel. However, this approach is unlike the full processing that requires full hardware replication. It exploits the presence of common operations between successive tokens. The performance of the proposed approach is better than sequential processing and approaches that of full parallel processing as the hardware resources are increased.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1083083Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1129
 P. Coussy, M. Meredith, D. Gajski, and A. Takach, "An Introduction to high-level synthesis," ," IEEE Design & Test of Comuters, vol. 26, no. 4, pp. 8-17, Aug. 2009.
 P.Coussy and A. Morawiec, High-Level Synthesis from Algorithm to Digital Circuit, Springer, 2008.
 H. Deman, J. Rabaey, P. Six, and L. Claesen, "Cathedral II: A silicon compiler for digital signal processing," IEEE Design & Test of Comuters, vol.3, no. 6, pp. 13-25, Dec. 1986.
 C.-T. Hwang, J.-H. Lee and Y.-C. Hsu, "A formal approach to the scheduling problem in high level synthesis," IEEE Trans. Computer- Aided Design Integrated Circuits Syst., vol.10, no. 4, pp. 464-475, 1991.
 F. F. Yassa, J.R. Jasica, R.L. Hartley, and S.E. Noujaim, "A silicon compiler for digital signal processing: Methodology, implementation, and applications," Proceedings of IEEE, vol. 75, no. 9, pp. 1272-1282, Sept. 1987.
 C.-Y. Wang and K.K Parhi, "High-level DSP synthesis using concurrent transformations, scheduling, and allocation," IEEE Trans. Computer- Aided Design Integrated Circuits Syst., vol. 14, no. 3, pp. 274-295, Mar. 1995.
 A. Shatnawi, J.Ghanim, and M. Ahmad, "High level synthesis of integrated heterogeneous pipelined processing elements for DSP applications," Computer and Electrical Engineering, vol. 30, no. 8, pp. 543-567, Nov. 2004.