@article{(Open Science Index):https://publications.waset.org/pdf/10001367, title = {Designing of Full Adder Using Low Power Techniques}, author = {Shashank Gautam}, country = {}, institution = {}, abstract = {This paper proposes techniques like MT CMOS, POWER GATING, DUAL STACK, GALEOR and LECTOR to reduce the leakage power. A Full Adder has been designed using these techniques and power dissipation is calculated and is compared with general CMOS logic of Full Adder. Simulation results show the validity of the proposed techniques is effective to save power dissipation and to increase the speed of operation of the circuits to a large extent. }, journal = {International Journal of Electronics and Communication Engineering}, volume = {9}, number = {4}, year = {2015}, pages = {983 - 987}, ee = {https://publications.waset.org/pdf/10001367}, url = {https://publications.waset.org/vol/100}, bibsource = {https://publications.waset.org/}, issn = {eISSN: 1307-6892}, publisher = {World Academy of Science, Engineering and Technology}, index = {Open Science Index 100, 2015}, }