Search results for: Zipper.

Authors: G. R. Nouri, H. Imani Kalesar, Zahra Ameli

Abstract:

Chevron frames (Inverted-V-braced frames or Vbraced frames) have seismic disadvantages, such as not good exhibit force redistribution capability and compression brace buckles immediately. Researchers developed new design provisions on increasing both the ductility and lateral resistance of these structures in seismic areas. One of these new methods is adding zipper columns, as proposed by Khatib et al. (1988) [2]. Zipper columns are vertical members connecting the intersection points of the braces above the first floor. In this paper applicability of the suspended zipper system to Seismic Rehabilitation of Steel Structures is investigated. The models are 3-, 6-, 9-, and 12-story Inverted-V-braced frames. In this case, it is assumed that the structures must be rehabilitated. For rehabilitation of structures, zipper column is used. The result of researches showed that the suspended zipper system is effective in case of 3-, 6-, and 9-story Inverted-V-braced frames and it would increase lateral resistance of structure up to life safety level. But in case of high-rise buildings (such as 12 story frame), it doesn-t show good performance. For solving this problem, the braced bay can consist of small “units" over the height of the entire structure, which each of them is a zipper-braced bay with a few stories. By using this method the lateral resistance of 12 story Inverted-V-braced frames is increased up to safety life level.

Keywords: chevron-braced frames, suspended zipper frames, zipper frames, zipper columns

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Authors: Reza Faghih Mirzaee, Mohammad Hossein Moaiyeri, Keivan Navi

Abstract:

In this paper we present two novel 1-bit full adder cells in dynamic logic style. NP-CMOS (Zipper) and Multi-Output structures are used to design the adder blocks. Characteristic of dynamic logic leads to higher speeds than the other standard static full adder cells. Using HSpice and 0.18┬Ám CMOS technology exhibits a significant decrease in the cell delay which can result in a considerable reduction in the power-delay product (PDP). The PDP of Multi-Output design at 1.8v power supply is around 0.15 femto joule that is 5% lower than conventional dynamic full adder cell and at least 21% lower than other static full adders.

Keywords: Bridge Style, Dynamic Logic, Full Adder, HighSpeed, Multi Output, NP-CMOS, Zipper.

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