@article{(Open Science Index):https://publications.waset.org/pdf/6440,
	  title     = {Interconnect Analysis of a Novel Multiplexer Based Full-Adder Cell for Power and Propagation Delay Optimizations},
	  author    = {G.Ramana Murthy and  C.Senthilpari and  P.Velrajkumar and  Lim Tien Sze},
	  country	= {},
	  institution	= {},
	  abstract     = {The proposed multiplexer-based novel 1-bit full
adder cell is schematized by using DSCH2 and its layout is generated
by using microwind VLSI CAD tool. The adder cell layout
interconnect analysis is performed by using BSIM4 layout analyzer.
The adder circuit is compared with other six existing adder circuits
for parametric analysis. The proposed adder cell gives better
performance than the other existing six adder circuits in terms of
power, propagation delay and PDP. The proposed adder circuit is
further analyzed for interconnect analysis, which gives better
performance than other adder circuits in terms of layout thickness,
width and height.},
	    journal   = {International Journal of Electronics and Communication Engineering},
	  volume    = {6},
	  number    = {8},
	  year      = {2012},
	  pages     = {815 - 819},
	  ee        = {https://publications.waset.org/pdf/6440},
	  url   	= {https://publications.waset.org/vol/68},
	  bibsource = {https://publications.waset.org/},
	  issn  	= {eISSN: 1307-6892},
	  publisher = {World Academy of Science, Engineering and Technology},
	  index 	= {Open Science Index 68, 2012},
	}