%0 Journal Article
	%A Reza Faghih Mirzaee and  Mohammad Hossein Moaiyeri and  Keivan Navi
	%D 2010
	%J International Journal of Electrical and Computer Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 39, 2010
	%T High Speed NP-CMOS and Multi-Output Dynamic Full Adder Cells
	%U https://publications.waset.org/pdf/2940
	%V 39
	%X In this paper we present two novel 1-bit full adder
cells in dynamic logic style. NP-CMOS (Zipper) and Multi-Output
structures are used to design the adder blocks. Characteristic of
dynamic logic leads to higher speeds than the other standard static
full adder cells. Using HSpice and 0.18┬Ám CMOS technology
exhibits a significant decrease in the cell delay which can result in a
considerable reduction in the power-delay product (PDP). The PDP
of Multi-Output design at 1.8v power supply is around 0.15 femto
joule that is 5% lower than conventional dynamic full adder cell and
at least 21% lower than other static full adders.
	%P 531 - 537