@article{(Open Science Index):https://publications.waset.org/pdf/2940,
	  title     = {High Speed NP-CMOS and Multi-Output Dynamic Full Adder Cells},
	  author    = {Reza Faghih Mirzaee and  Mohammad Hossein Moaiyeri and  Keivan Navi},
	  country	= {},
	  institution	= {},
	  abstract     = {In this paper we present two novel 1-bit full adder
cells in dynamic logic style. NP-CMOS (Zipper) and Multi-Output
structures are used to design the adder blocks. Characteristic of
dynamic logic leads to higher speeds than the other standard static
full adder cells. Using HSpice and 0.18┬Ám CMOS technology
exhibits a significant decrease in the cell delay which can result in a
considerable reduction in the power-delay product (PDP). The PDP
of Multi-Output design at 1.8v power supply is around 0.15 femto
joule that is 5% lower than conventional dynamic full adder cell and
at least 21% lower than other static full adders.},
	    journal   = {International Journal of Electrical and Computer Engineering},
	  volume    = {4},
	  number    = {3},
	  year      = {2010},
	  pages     = {531 - 537},
	  ee        = {https://publications.waset.org/pdf/2940},
	  url   	= {https://publications.waset.org/vol/39},
	  bibsource = {https://publications.waset.org/},
	  issn  	= {eISSN: 1307-6892},
	  publisher = {World Academy of Science, Engineering and Technology},
	  index 	= {Open Science Index 39, 2010},