A Novel Low Power, High Speed 14 Transistor CMOS Full Adder Cell with 50% Improvement in Threshold Loss Problem

Authors: T. Vigneswaran, B. Mukundhan, P. Subbarami Reddy

Abstract:

Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. In addition to its main task, which is adding two numbers, it participates in many other useful operations such as subtraction, multiplication, division,, address calculation,..etc. In most of these systems the adder lies in the critical path that determines the overall speed of the system. So enhancing the performance of the 1-bit full adder cell (the building block of the adder) is a significant goal.Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose a new low power adder cell by sacrificing the MOS Transistor count that reduces the serious threshold loss problem, considerably increases the speed and decreases the power when compared to the static energy recovery full (SERF) adder. So a new improved 14T CMOS l-bit full adder cell is presented in this paper. Results show 50% improvement in threshold loss problem, 45% improvement in speed and considerable power consumption over the SERF adder and other different types of adders with comparable performance.

Keywords: Arithmetic circuit, full adder, multiplier, low power, very Large-scale integration (VLSI).

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1075388

References:

[1] Nan Zhuang and Haomin Wu, "A new design of the CMOS full adder" IEEE Journal of Solid State Circuits, Vol. 27, No.5, pp. 840-844, May 1992.
[2] V. G. Oklobdzija, M Soderstrand and B.Duchene "Development and Synthesis Method for Pass-Transistor Logic Family for High-Speed and Low Power CMOS" Proceedings of the 1995 IEEE 38th Midwest Symposium on Circuits and Systems, Rio de Janeiro, 1995.
[3] R. Shalem, E. John, and L. K. John, "A novel low power energy recovery full adder cell," in Proc. IEEE Great Lakes VLSI Symp., Feb. 1999, pp. 380-383.
[4] N. Weste and K. Eshraghian, "Principles of CMOSVLSI Design", A System Perspective. Reading, MA: Addison-Wesley, 1993.
[5] R. Zimmermann and W. Fichtner, "Low-power logic styles: CMOS versus pass-transistor logic," IEEE J. Solid-State Circuits, vol. 32, pp.1079-1090, July 1997.
[6] T. Callaway and E. Swartzlander, Jr., "Low power arithmetic components," IEEE in Low Power Design Methodologies. Norwell, MA: Kluwer, 1996, pp. 161-201.
[7] A.Chandrakasan,"Low-power CMOS digital design," IEEE JSSC", vol.27, pp.473-484, Apr.1992.
[8] Ahmed M. Shams and Magdy A. Bayoumi, "A New Full Adder Cell for low-power Applications", Proceedings of the IEEE Great Lakes Symposium on VLSI, 1998, pp. 45-49.
[9] JohnRabaey, "Digital integrated circuits", Second Edison, 2003.
[10] K. P. Parhi, "Fast Low-Energy VLSI Binary Addition", Proceedings of the International Conference on Computer Design, 1997, pp.676-684.
[11] Gerard M. Blair, "Designing low power CMOS", IEEE Electronics & Communication Engineering Joumal, vol. 6, pp. 229-236, October 1994.