Search results for: Gate tunneling current

Authors: A. A. Akande, B. P. Dhonge, B. W. Mwakikunga, A. G. J. Machatine

Abstract:

This article presents gate-voltage controlled humidity sensing performance of vanadium dioxide nanoparticles prepared from NH₄VO₃ precursor using microwave irradiation technique. The X-ray diffraction, transmission electron diffraction, and Raman analyses reveal the formation of VO₂ (B) with V₂O₅ and an amorphous phase. The BET surface area is found to be 67.67 m²/g. The humidity sensing measurements using the patented lateral-gate MOSFET configuration was carried out. The results show the optimum response at 5 V up to 8 V of gate voltages for 10 to 80% of relative humidity. The dose-response equation reveals the enhanced resilience of the gated VO₂ sensor which may saturate above 272% humidity. The response and recovery times are remarkably much faster (about 60 s) than in non-gated VO₂ sensors which normally show response and recovery times of the order of 5 minutes (300 s).

Keywords: VO2, VO2 (B), V2O5, MOSFET, gate voltage, humidity sensor.

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Authors: Spyridon Nikolaidis

Abstract:

A modeling approach for CMOS gates is presented based on the use of the equivalent inverter. A new model for the inverter has been developed using a simplified transistor current model which incorporates the nanoscale effects for the planar technology. Parametric expressions for the output voltage are provided as well as the values of the output and supply current to be compatible with the CCS technology. The model is parametric according the input signal slew, output load, transistor widths, supply voltage, temperature and process. The transistor widths of the equivalent inverter are determined by HSPICE simulations and parametric expressions are developed for that using a fitting procedure. Results for the NAND gate shows that the proposed approach offers sufficient accuracy with an average error in propagation delay about 5%.

Keywords: CMOS gate modeling, Inverter modeling, transistor current model, timing model.

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Authors: Xiang Li, Zhixian Chen, Zheng Fang, Aashit Kamath, Xinpeng Wang, Navab Singh, Guo-Qiang Lo, Dim-Lee Kwong

Abstract:

We integrate TiN/Ni/HfO2/Si RRAM cell with a vertical gate-all-around (GAA) nanowire transistor to achieve compact 4F2 footprint in a 1T1R configuration. The tip of the Si nanowire (source of the transistor) serves as bottom electrode of the memory cell. Fabricated devices with nanowire diameter ~ 50nm demonstrate ultra-low current/power switching; unipolar switching with 10μA/30μW SET and 20μA/30μW RESET and bipolar switching with 20nA/85nW SET and 0.2nA/0.7nW RESET. Further, the switching current is found to scale with nanowire diameter making the architecture promising for future scaling.

Keywords: RRAM, 1T1R, gate-all-around FET, nanowire FET, vertical MOSFETs

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Authors: Jae-Chang Kwak, Yong-Seo Koo

Abstract:

The high efficiency power management IC (PMIC) with switching device is presented in this paper. PMIC is controlled with PFM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS (DT-CMOS) with low on-resistance is designed to decrease conduction loss. The threshold voltage of DT-CMOS drops as the gate voltage increase, resulting in a much higher current handling capability than standard MOSFET. PFM control circuits consist of a generator, AND gate and comparator. The generator is made to have 1.2MHz oscillation voltage. The DC-DC converter based on PFM control circuit and low on-resistance switching device is presented in this paper.

Keywords: DT-CMOS, PMIC, PFM, DC-DC converter.

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Authors: Osamu Igawa, Hiroshi Kouchiwa, Yuji Ito

Abstract:

In recent years, a reconstruction project for sewer  pipelines has been progressing in Japan with the aim of renewing old  sewer culverts. However, it is difficult to secure a sufficient base area  for shafts in an urban area because many streets are narrow with a  complex layout. As a result, construction in such urban areas is  generally very demanding.  In urban areas, there is a strong requirement for a safe, reliable and  economical construction method that does not disturb the public’s  daily life and urban activities. With this in mind, we developed a new  construction method called the “shield switching type micro-tunneling  method,” which integrates the micro-tunneling method and shield  method.  In this method, pipeline is constructed first for sections that are  gently curved or straight using the economical micro-tunneling  method, and then the method is switched to the shield method for  sections with a sharp curve or a series of curves without establishing  an intermediate shaft.  This paper provides the information, features and construction  examples of this newly developed method.

 

Keywords: Micro-tunneling method, Secondary lining applied RC segment, Sharp curve, Shield method, Switching type.

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Authors: M. M. Karkhanehchi, A. Ammani

Abstract:

A simple analytical model has been developed to optimize biasing conditions for obtaining maximum linearity among lattice-matched, pseudomorphic and metamorphic HEMT types as well as enhancement and depletion HEMT modes. A nonlinear current-voltage model has been simulated based on extracted data to study and select the most appropriate type and mode of HEMT in terms of a given gate-source biasing voltage within the device so as to employ the circuit for the highest possible output current or voltage linear swing. Simulation results can be used as a basis for the selection of optimum gate-source biasing voltage for a given type and mode of HEMT with regard to a circuit design. The consequences can also be a criterion for choosing the optimum type or mode of HEMT for a predetermined biasing condition.

Keywords: Biasing, characteristic, linearity, simulation.

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Authors: Pil Seong Park

Abstract:

Homemade HPC clusters are widely used in many small labs, because they are easy to build and cost-effective. Even though incremental growth is an advantage of clusters, it results in heterogeneous systems anyhow. Instead of adding new nodes to the cluster, we can extend clusters to include some other Internet servers working independently on the same LAN, so that we can make use of their idle times, especially during the night. However extension across a firewall raises some security problems with NFS. In this paper, we propose a method to solve such a problem using SSH tunneling, and suggest a modified structure of the cluster that implements it.

Keywords: Extension of HPC clusters, Security, NFS, SSH tunneling.

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Authors: Hai-Qing Xie, Yun Zeng, Yong-Hong Yan, Guo-Liang Zhang, Tai-Hong Wang

Abstract:

We propose photo-BJMOSFET (Bipolar Junction Metal-Oxide-Semiconductor Field Effect Transistor) fabricated on SOI film. ITO film is adopted in the device as gate electrode to reduce light absorption. I-V characteristics of photo-BJMOSFET obtained in dark (dark current) and under 570nm illumination (photo current) are studied furthermore to achieve high photo-to-dark-current contrast ratio. Two variables in the calculation were the channel length and the thickness of the film which were set equal to six different values, i.e., L=2, 4, 6, 8, 10, and 12μm and three different values, i.e., dsi =100, 200 and 300nm, respectively. The results indicate that the greatest photo-to-dark-current contrast ratio is achieved with L=10μm and dsi=200 nm at VGK=0.6V.

Keywords: Photo-to-dark-current contrast ratio, Photo-current, Dark-current, Process parameter

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Authors: Rekha V. Dundur , M.V.Latte, S.Y. Kulkarni, M.K.Venkatesha

Abstract:

The advent of multi-million gate Field Programmable Gate Arrays (FPGAs) with hardware support for multiplication opens an opportunity to recreate a significant portion of the front end of a human cochlea using this technology. In this paper we describe the implementation of the cochlear filter and show that it is entirely suited to a single device XC3S500 FPGA implementation .The filter gave a good fit to real time data with efficiency of hardware usage.

Keywords: Cochlea, FPGA, IIR (Infinite Impulse Response), Multiplier.

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Authors: Tapas Kumar Sinha, Joseph Mathew

Abstract:

Based on the Lagrangian for the Gross –Pitaevskii equation as derived by H. Sakaguchi and B.A Malomed [5] we have derived a double well model for the nonlinear optical lattice. This model explains the various features of nonlinear optical lattices. Further, from this model we obtain and simulate the probability for tunneling from one well to another which agrees with experimental results [4].

Keywords: Double well model, nonlinear optical lattice, Solitons, tunneling.

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Authors: Hai-Qing Xie, Yun Zeng, Yong-Hong Yan, Jian-Ping Zeng, Tai-Hong Wang

Abstract:

Photo-BJMOSFET (Bipolar Junction Metal-Oxide- Semiconductor Field Effect Transistor) fabricated on SOI film was proposed. ITO film is adopted in the device as gate electrode to reduce light absorption. Depletion region but not inversion region is formed in film by applying gate voltage (but low reverse voltage) to achieve high photo-to-dark-current ratio. Comparisons of photoelectriccharacteristics executed among VGK=0V, 0.3V, 0.6V, 0.9V and 1.0V (reverse voltage VAK is equal to 1.0V for total area of 10×10μm2). The results indicate that the greatest improvement in photo-to-dark-current ratio is achieved up to 2.38 at VGK=0.6V. In addition, photo-BJMOSFET is compatible with CMOS integration due to big input resistance

Keywords: Photo-BJMOSFET, Responsivity, Sensitivity, Spectral response.

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Authors: Shobha Sharma, Amita Dev

Abstract:

Data driven dynamic logic is the high speed dynamic circuit with low area. The clock of the dynamic circuit is removed and data drives the circuit instead of clock for precharging purpose. This data driven dynamic nand gate is given static forward substrate biasing of Vsupply/2 as well as the substrate bias is connected to the input data, resulting in dynamic substrate bias. The dynamic substrate bias gives the shortest propagation delay with a penalty on the power dissipation. Propagation delay is reduced by 77.8% compared to the normal reverse substrate bias Data driven dynamic nand. Also dynamic substrate biased D3nand’s propagation delay is reduced by 31.26% compared to data driven dynamic nand gate with static forward substrate biasing of Vdd/2. This data driven dynamic nand gate with dynamic body biasing gives us the highest speed with no area penalty and finds its applications where power penalty is acceptable. Also combination of Dynamic and static Forward body bias can be used with reduced propagation delay compared to static forward biased circuit and with comparable increase in an average power. The simulations were done on hspice simulator with 22nm High-k metal gate strained Si technology HP models of Arizona State University, USA.

Keywords: Data driven nand gate, dynamic substrate biasing, nand gate, static substrate biasing.

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Authors: Z. Dibi, F. Djeffal, N. Lakhdar

Abstract:

In this paper, we have developed an explicit analytical drain current model comprising surface channel potential and threshold voltage in order to explain the advantages of the proposed Gate Stack Double Diffusion (GSDD) MOSFET design over the conventional MOSFET with the same geometric specifications that allow us to use the benefits of the incorporation of the high-k layer between the oxide layer and gate metal aspect on the immunity of the proposed design against the self-heating effects. In order to show the efficiency of our proposed structure, we propose the simulation of the power chopper circuit. The use of the proposed structure to design a power chopper circuit has showed that the (GSDD) MOSFET can improve the working of the circuit in terms of power dissipation and self-heating effect immunity. The results so obtained are in close proximity with the 2D simulated results thus confirming the validity of the proposed model.

Keywords: Double-Diffusion, modeling, MOSFET, power.

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Authors: Cheng-Hsien Chang, Jyi-Tsong Lin, Po-Hsieh Lin, Hung-Pei Hsu, Chan-Hsiang Chang, Ming-Tsung Shih, Shih-Chuan Tseng, Min-Yan Lin

Abstract:

In this paper, we have proposed a novel FinFET with extended body under the poly gate, which is called EB-FinFET, and its characteristic is demonstrated by using three-dimensional (3-D) numerical simulation. We have analyzed and compared it with conventional FinFET. The extended body height dependence on the drain induced barrier lowering (DIBL) and subthreshold swing (S.S) have been also investigated. According to the 3-D numerical simulation, the proposed structure has a firm structure, an acceptable short channel effect (SCE), a reduced series resistance, an increased on state drain current (I on) and a large normalized I DS. Furthermore, the structure can also improve corner effect and reduce self-heating effect due to the extended body. Our results show that the EBFinFET is excellent for nanoscale device.

Keywords: SOI, FinFET, tri-gate, self-heating effect.

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Authors: A. Hamdoune, M. Abdelmoumene, A. Hamroun

Abstract:

The objective of this paper is to simulate static I-V and dynamic characteristics of an appropriated and recessed n-GaN/AlxGa1-xN/GaN high electron mobility (HEMT). Using SILVACO TCAD device simulation, and optimized technological parameters; we calculate the drain-source current (lDS) as a function of the drain-source voltage (VDS) for different values ​​of the gate-source voltage (VGS), and the drain-source current (lDS) depending on the gate-source voltage (VGS) for a drain-source voltage (VDS) of 20 V, for various temperatures. Then, we calculate the cut-off frequency and the maximum oscillation frequency for different temperatures.

We obtain a high drain-current equal to 60 mA, a low knee voltage (Vknee) of 2 V, a high pinch-off voltage (VGS0) of 53.5 V, a transconductance greater than 600 mS/mm, a cut-off frequency (f_T) of about 330 GHz, and a maximum oscillation frequency (fmax) of about 1 THz.

Keywords: n-GaN/AlGaN/GaN HEMT, drain-source current (IDS), transconductance (gm), cut-off frequency (fT), maximum oscillation frequency (fmax).

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Authors: Min-ju Kwon, Chae-won Kim, Jeong-yun Seo, Hee-guk Chae, Yong-seo Koo

Abstract:

In this paper, we presented the LDO (low-dropout) regulator which enhanced the PSRR by applying the constant current source generation technique through the BGR (Band Gap Reference) to form the noise sensing circuit. The current source through the BGR has a constant current value even if the applied voltage varies. Then, the noise sensing circuit, which is composed of the current source through the BGR, operated between the error amplifier and the pass transistor gate of the LDO regulator. As a result, the LDO regulator has a PSRR of -68.2 dB at 1k Hz, -45.85 dB at 1 MHz and -45 dB at 10 MHz. the other performance of the proposed LDO was maintained at the same level of the conventional LDO regulator.

Keywords: LDO regulator, noise sensing circuit, current reference, pass transistor.

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Authors: Indre Brazauskaite, Vilte Auruskeviciene

Abstract:

The paper explores the Stage-Gate framework application for innovation maturity among small and medium-sized enterprises (SMEs). Innovation management becomes an essential business survival process for all sizes of organizations that can be evaluated and audited systemically. This research systemically defines and assesses the innovation process from the perspective of the company’s top management. Empirical research explores attitudes and existing practices of innovation management in SMEs in Baltic countries. It structurally investigates the current innovation management practices, level of standardization, and potential challenges in the area. Findings allow to structure of existing practices based on an institutionalized model and contribute to a more advanced understanding of the innovation process among SMEs. Practically, findings contribute to advanced decision-making and business planning in the process.

Keywords: innovation measure, innovation process, small and medium-sized enterprises, SMEs, stage-gate framework.

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Authors: A. R. Salimi, M. Esmaeili, B. Salehi

Abstract:

The development and extension of large cities induced a need for shallow tunnel in soft ground of building areas. Estimation of ground settlement caused by the tunnel excavation is important engineering point. In this paper, prediction of surface subsidence caused by tunneling in one section of seventh line of Tehran subway is considered. On the basis of studied geotechnical conditions of the region, tunnel with the length of 26.9km has been excavated applying a mechanized method using an EPB-TBM with a diameter of 9.14m. In this regard, settlement is estimated utilizing both analytical and numerical finite element method. The numerical method shows that the value of settlement in this section is 5cm. Besides, the analytical consequences (Bobet and Loganathan-Polous) are 5.29 and 12.36cm, respectively. According to results of this study, due tosaturation of this section, there are good agreement between Bobet and numerical methods. Therefore, tunneling processes in this section needs a special consolidation measurement and support system before the passage of tunnel boring machine.

Keywords: TBM, Subsidence, Numerical Method, Analytical Method.

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Authors: Omid Mirmotahari, Yngvar Berg, Ahmad Habibizad Navin

Abstract:

Reversible logic is becoming more and more prominent as the technology sets higher demands on heat, power, scaling and stability. Reversible gates are able at any time to "undo" the current step or function. Multiple-valued logic has the advantage of transporting and evaluating higher bits each clock cycle than binary. Moreover, we demonstrate in this paper, combining these disciplines we can construct powerful multiple-valued reversible logic structures. In this paper a reversible block implemented by pseudo floatinggate can perform AD-function and a DA-function as its reverse application.

Keywords: Reversible logic, bi-directional, Pseudo floating-gate(PFG), multiple-valued logic (MVL).

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Authors: S. Boughanem, D. A. Jesson, M. J. Mulheron, P.A. Smith C. Eddie, S. Psomas, M. Rimes

Abstract:

Cements, which are intrinsically brittle materials, can exhibit a degree of pseudo-ductility when reinforced with a sufficient volume fraction of a fibrous phase. This class of materials, called Engineered Cement Composites (ECC) has the potential to be used in future tunneling applications where a level of pseudo-ductility is required to avoid brittle failures. However uncertainties remain regarding mechanical performance. Previous work has focused on comparatively thin specimens; however for future civil engineering applications, it is imperative that the behavior in tension of thicker specimens is understood. In the present work, specimens containing cement powder and admixtures have been manufactured following two different processes and tested in tension. Multiple matrix cracking has been observed during tensile testing, leading to a “strain-hardening" behavior, confirming the possible suitability of ECC material when used as thick sections (greater than 50mm) in tunneling applications.

Keywords: Cement composite, polymeric fibers, pseudoductility, test-geometry.

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Authors: Chih Chin Yang, Yen Chun Lin, Hsiao Hsuan Cheng

Abstract:

Three similar negative differential resistance (NDR) profiles with both high peak to valley current density ratio (PVCDR) value and high peak current density (PCD) value in unity resonant tunneling electronic circuit (RTEC) element is developed in this paper. The PCD values and valley current density (VCD) values of the three NDR curves are all about 3.5 A and 0.8 A, respectively. All PV values of NDR curves are 0.40 V, 0.82 V, and 1.35 V, respectively. The VV values are 0.61 V, 1.07 V, and 1.69 V, respectively. All PVCDR values reach about 4.4 in three NDR curves. The PCD value of 3.5 A in triple PVCDR RTEC element is better than other resonant tunneling devices (RTD) elements. The high PVCDR value is concluded the lower VCD value about 0.8 A. The low VCD value is achieved by suitable selection of resistors in triple PVCDR RTEC element. The low PV value less than 1.35 V possesses low power dispersion in triple PVCDR RTEC element. The designed multiple value logical level (MVLL) system using triple PVCDR RTEC element provides equidistant logical level. The logical levels of MVLL system are about 0.2 V, 0.8 V, 1.5 V, and 2.2 V from low voltage to high voltage and then 2.2 V, 1.3 V, 0.8 V, and 0.2 V from high voltage back to low voltage in half cycle of sinusoid wave. The output level of four levels MVLL system is represented in 0.3 V, 1.1 V, 1.7 V, and 2.6 V, which satisfies the NMP condition of traditional two-bit system. The remarkable logical characteristic of improved MVLL system with paralleled capacitor are with four significant stable logical levels about 220 mV, 223 mV, 228 mV, and 230 mV. The stability and articulation of logical levels of improved MVLL system are outstanding. The average holding time of improved MVLL system is approximately 0.14 μs. The holding time of improved MVLL system is fourfold than of basic MVLL system. The function of additional capacitor in the improved MVLL system is successfully discovered.

Keywords: Capacitance, Logical level, Constant current source

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Authors: Santanu Santra, Utpal Roy

Abstract:

The most important mathematical operation for any computing system is addition. An efficient adder can be of greater assistance in designing of any arithmetic circuits. Quantum-dot Cellular Automata (QCA) is a promising nanotechnology to create electronic circuits for computing devices and suitable candidate for next generation of computing systems. The article presents a modest approach to implement a novel XOR gate. The gate is simple in structure and powerful in terms of implementing digital circuits. By applying the XOR gate, the hardware requirement for a QCA circuit can be decrease and circuits can be simpler in level, clock phase and cell count. In order to verify the functionality of the proposed device some implementation of Half Adder (HA) and Full Adder (FA) is checked by means of computer simulations using QCA-Designer tool. Simulation results and physical relations confirm its usefulness in implementing every digital circuit.

Keywords: Clock, Computing system, Majority gate, QCA, QCA Designer.

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Authors: Z. X. Chen, N. Singh, D.-L. Kwong

Abstract:

This paper presents a vertical silicon nanowire n- MOSFET integrated with a CMOS-compatible fully-silicided (FUSI) NiSi2 gate. Devices with nanowire diameter of 50nm show good electrical performance (SS < 70mV/dec, DIBL < 30mV/V, Ion/Ioff > 107). Most significantly, threshold voltage tunability of about 0.2V is shown. Although threshold voltage remains low for the 50nm diameter device, it is expected to become more positive as nanowire diameter reduces.

Keywords: NiSi , fully-silicided (FUSI) gate, vertical siliconnanowire (SiNW), CMOS compatible.

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Authors: Kittipong Tripetch, Nobuhiko Nakano

Abstract:

Two types of floating active resistors based on a complementary regulated cascode topology with cross-coupled regulated transistors are presented in this paper. The first topology is a high swing complementary regulated cascode active resistor. The second topology is a complementary common gate with a regulated cross coupled transistor. The small-signal input resistances of the floating resistors are derived. Three graphs of the input current versus the input voltage for different aspect ratios are designed and plotted using the Cadence Spectre 0.18-µm Rohm Semiconductor process. The total harmonic distortion graphs are plotted for three different aspect ratios with different input-voltage amplitudes and different input frequencies. From the simulation results, it is observed that a resistance of approximately 8.52 MΩ can be obtained from supply voltage at  ±0.9 V.

Keywords: Complementary common gate, complementary regulated cascode, current mirror, floating active resistors.

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Authors: Hani Baek, Gwang Min Sun, Chansun Shin, Sung Ho Ahn

Abstract:

Fast neutron irradiation using nuclear reactors is an effective method to improve switching loss and short circuit durability of power semiconductor (insulated gate bipolar transistors (IGBT) and insulated gate transistors (IGT), etc.). However, not only fast neutrons but also thermal neutrons, epithermal neutrons and gamma exist in the nuclear reactor. And the electrical properties of the IGBT may be deteriorated by the irradiation of gamma. Gamma irradiation damages are known to be caused by Total Ionizing Dose (TID) effect and Single Event Effect (SEE), Displacement Damage. Especially, the TID effect deteriorated the electrical properties such as leakage current and threshold voltage of a power semiconductor. This work can confirm the effect of the gamma irradiation on the electrical properties of 600 V NPT-IGBT. Irradiation of gamma forms lattice defects in the gate oxide and Si-SiO₂ interface of the IGBT. It was confirmed that this lattice defect acts on the center of the trap and affects the threshold voltage, thereby negatively shifted the threshold voltage according to TID. In addition to the change in the carrier mobility, the conductivity modulation decreases in the n-drift region, indicating a negative influence that the forward voltage drop decreases. The turn-off delay time of the device before irradiation was 212 ns. Those of 2.5, 10, 30, 70 and 100 kRad(Si) were 225, 258, 311, 328, and 350 ns, respectively. The gamma irradiation increased the turn-off delay time of the IGBT by approximately 65%, and the switching characteristics deteriorated.

Keywords: NPT-IGBT, gamma irradiation, switching, turn-off delay time, recombination, trap center.

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Authors: Rishikesh Pandey, Maneesha Gupta

Abstract:

A new low-voltage floating gate MOSFET (FGMOS) based squarer using square law characteristic of the FGMOS is proposed in this paper. The major advantages of the squarer are simplicity, rail-to-rail input dynamic range, low total harmonic distortion, and low power consumption. The proposed circuit is biased without body effect. The circuit is designed and simulated using SPICE in 0.25μm CMOS technology. The squarer is operated at the supply voltages of ±0.75V . The total harmonic distortion (THD) for the input signal 0.75Vpp at 25 KHz, and maximum power consumption were found to be less than 1% and 319μW respectively.

Keywords: Analog signal processing, floating gate MOSFETs, low-voltage, Spice, squarer.

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Authors: Mojtaba Ghodsi, Hamidreza Ziaifar, Morteza Mohammadzaheri, Payam Soltani

Abstract:

In this paper, the performance of a medium power (25 kW/25 kHz) hybrid inverter with a reactive transformer is investigated. To analyze the sensitivity of the inverster, the RSM technique is employed to manifest the effective factors in the inverter to minimize current passing through the Insulated Bipolar Gate Transistors (IGBTs) (current stress). It is revealed that the ratio of the axillary inductor to the effective inductance of resonant inverter (N), is the most effective parameter to minimize the current stress in this type of inverter. In practice, proper selection of N mitigates the current stress over IGBTs by five times. This reduction is very helpful to keep the IGBTs at normal temperatures.

Keywords: Analytical analysis, hybrid resonant inverter, reactive transformer, response surface method.

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Authors: P. Jelodarian , E. Farshidi

Abstract:

In this paper, a new approach for design of a fully differential second order current mode continuous-time sigma-delta modulator is presented. For circuit implementation, square root domain (SRD) translinear loop based on floating-gate MOS transistors that operate in saturation region is employed. The modulator features, low supply voltage, low power consumption (8mW) and high dynamic range (55dB). Simulation results confirm that this design is suitable for data converters.

Keywords: Sigma-delta, current-mode, translinear loop, geometric mean, squarer/divider.

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Authors: H. Paredes Gutiérrez, S. T. Pérez-Merchancano

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Motivated by recent experimental and theoretical developments, we investigate the influence of embedded quantum dot (EQD) of different geometries (lens, ring and pyramidal) in a double barrier heterostructure (DBH). We work with a general theory of quantum transport that accounts the tight-binding model for the spin dependent resonant tunneling in a semiconductor nanostructure, and Rashba spin orbital to study the spin orbit coupling. In this context, we use the second quantization theory for Rashba effect and the standard Green functions method. We calculate the current density as a function of the voltage without and in the presence of quantum dots. In the second case, we considered the size and shape of the quantum dot, and in the two cases, we worked considering the spin polarization affected by external electric fields. We found that the EQD generates significant changes in current when we consider different morphologies of EQD, as those described above. The first thing shown is that the current decreases significantly, such as the geometry of EQD is changed, prevailing the geometrical confinement. Likewise, we see that the current density decreases when the voltage is increased, showing that the quantum system studied here is more efficient when the morphology of the quantum dot changes.

Keywords: Quantum semiconductors, nanostructures, quantum dots, spin polarization.

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Authors: Vijaya K. Srivastava, Davide Spinello

Abstract:

This paper presents performance of two robust gradient-based heuristic optimization procedures based on 3ⁿ enumeration and tunneling approach to seek global optimum of constrained integer problems. Both these procedures consist of two distinct phases for locating the global optimum of integer problems with a linear or non-linear objective function subject to linear or non-linear constraints. In both procedures, in the first phase, a local minimum of the function is found using the gradient approach coupled with hemstitching moves when a constraint is violated in order to return the search to the feasible region. In the second phase, in one optimization procedure, the second sub-procedure examines 3ⁿ integer combinations on the boundary and within hypercube volume encompassing the result neighboring the result from the first phase and in the second optimization procedure a tunneling function is constructed at the local minimum of the first phase so as to find another point on the other side of the barrier where the function value is approximately the same. In the next cycle, the search for the global optimum commences in both optimization procedures again using this new-found point as the starting vector. The search continues and repeated for various step sizes along the function gradient as well as that along the vector normal to the violated constraints until no improvement in optimum value is found. The results from both these proposed optimization methods are presented and compared with one provided by popular MS Excel solver that is provided within MS Office suite and other published results.

Keywords: Constrained integer problems, enumerative search algorithm, Heuristic algorithm, tunneling algorithm.

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